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DESCRIPTION
The WM9715L is a highly integrated input / output device designed for mobile computing and communications. The device can connect directly to a 4-wire or 5-wire touchpanel, mono or stereo microphones, stereo headphones and a mono speaker, reducing total component count in the system. Additionally, phone input and output pins are provided for seamless integration with wireless communication devices. The WM9715L also offers up to four auxiliary ADC inputs for analogue measurements such as temperature or light. To monitor the battery voltage in portable systems, the WM9715L has two uncommitted comparator inputs. All device functions are accessed and controlled through a single AC-Link interface compatible with the AC'97 standard (rev 2.2). Additionally, the WM9715L can generate interrupts to indicate pen down, pen up, availability of touchpanel data, low battery, and dead battery. The WM9715L operates at supply voltages from 1.8 to 3.6 Volts. Each section of the chip can be powered down under software control to save power. The device is available in a small leadless 7x7mm QFN package, ideal for use in handheld portable systems.
WM9715L
AC'97 Audio and Touchpanel CODEC
FEATURES
* AC'97 Rev 2.2 compatible stereo codec - DAC SNR 90dB, THD -86dB - ADC SNR 88dB, THD -88dB - Variable Rate Audio, supports all WinCE sample rates - Tone Control, Bass Boost and 3D Enhancement * On-chip 45mW headphone driver * On-chip 400mW mono speaker driver * Stereo, mono or differential microphone input - Automatic Level Control (ALC) * Auxiliary mono DAC (ring tone or DC level generation) * Seamless interface to wireless chipset * Resistive touchpanel interface - Supports 4-wire and 5-wire panels - 12-bit resolution, INL 3 LSBs (<0.5 pixels) - X, Y and touch-pressure (Z) measurement - Pen-down detection supported in Sleep Mode * 2 comparator inputs for battery monitoring * Up to 4 auxiliary ADC inputs * 1.8V to 3.6V supplies * 7x7mm QFN
APPLICATIONS
* Personal Digital Assistants (PDA) * Smartphones * Handheld and Tablet Computers
BLOCK DIAGRAM
Y-/BL
XTLOUT
X-/TL
PENDOWN
X+/BR
Y+/TR
TPGND TPVDD
BITCLK SYNC SDATAIN SDATAOUT RESETB
WIPER/ AUX4
WOLFSON MICROELECTRONICS plc
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SPDIF_OUT
ADCIRQ GENIRQ
XTLIN
Production Data, December 2007, Rev 4.0 Copyright (c)2007 Wolfson Microelectronics plc.
WM9715L TABLE OF CONTENTS
Production Data
DESCRIPTION .......................................................................................................1 FEATURES.............................................................................................................1 APPLICATIONS .....................................................................................................1 BLOCK DIAGRAM .................................................................................................1 TABLE OF CONTENTS .........................................................................................2 PIN CONFIGURATION...........................................................................................4 ORDERING INFORMATION ..................................................................................4 PIN DESCRIPTION ................................................................................................5 ABSOLUTE MAXIMUM RATINGS.........................................................................6 RECOMMENDED OPERATING CONDITIONS .....................................................6 ELECTRICAL CHARACTERISTICS ......................................................................7
AUDIO OUTPUTS.......................................................................................................... 7 AUDIO INPUTS.............................................................................................................. 8 AUXILIARY MONO DAC (AUXDAC).............................................................................. 8 TOUCHPANEL AND AUXILIARY ADC .......................................................................... 9 COMPARATORS ........................................................................................................... 9 REFERENCE VOLTAGES ........................................................................................... 10 DIGITAL INTERFACE CHARACTERISTICS................................................................ 10 HEADPHONE / SPEAKER OUTPUT THD VERSUS POWER ..................................... 11 POWER CONSUMPTION............................................................................................ 12
DEVICE DESCRIPTION.......................................................................................13
INTRODUCTION.......................................................................................................... 13 AUDIO PATHS OVERVIEW......................................................................................... 14
AUDIO INPUTS ....................................................................................................15
LINE INPUT ................................................................................................................. 15 MICROPHONE INPUT................................................................................................. 15 PHONE INPUT............................................................................................................. 17 PCBEEP INPUT ........................................................................................................... 18
AUDIO ADC..........................................................................................................19
RECORD SELECTOR ................................................................................................. 20 RECORD GAIN............................................................................................................ 21 AUTOMATIC LEVEL CONTROL.................................................................................. 22
AUDIO DACS .......................................................................................................25
STEREO DAC.............................................................................................................. 25 AUXILIARY DAC.......................................................................................................... 28
ANALOGUE AUDIO OUTPUTS ...........................................................................30
HEADPHONE OUTPUTS - HPOUTL AND HPOUTR.................................................. 30 EAR SPEAKER OUTPUT - OUT3............................................................................... 31 LOUDSPEAKER OUTPUTS - LOUT2 AND ROUT2.................................................... 32 PHONE OUTPUT (MONOOUT)................................................................................... 33 THERMAL SENSOR .................................................................................................... 33 DIGITAL AUDIO (SPDIF) OUTPUT ............................................................................. 34 AUDIO MIXERS ........................................................................................................... 35
VARIABLE RATE AUDIO / SAMPLE RATE CONVERSION ...............................37
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WM9715L TOUCHPANEL INTERFACE................................................................................38
PRINCIPLE OF OPERATION - FOUR-WIRE TOUCHPANEL ..................................... 38 PRINCIPLE OF OPERATION - FIVE-WIRE TOUCHPANEL........................................ 40 CONTROLLING THE TOUCHPANEL DIGITISER ....................................................... 42
AUXILIARY ADC INPUTS ....................................................................................47
BATTERY MEASUREMENT USING THE BMON/AUX3 PIN ....................................... 47
BATTERY ALARM AND ANALOGUE COMPARATORS ....................................48 INTERRUPT CONTROL.......................................................................................51
THE ADCIRQ PIN ........................................................................................................ 51 THE PENDOWN PIN ................................................................................................... 51 THE GENIRQ PIN........................................................................................................ 51
POWER MANAGEMENT .....................................................................................54
UNUSED ANALOGUE INPUTS AND OUTPUTS ......................................................... 57
AC97 DATA AND CONTROL INTERFACE .........................................................58
INTERFACE PROTOCOL............................................................................................ 58 INTERFACE TIMING ................................................................................................... 59
REGISTER MAP...................................................................................................62
REGISTER BITS BY ADDRESS .................................................................................. 63
APPLICATIONS INFORMATION .........................................................................72
RECOMMENDED EXTERNAL COMPONENTS........................................................... 72 RECOMMENDED COMPONENTS VALUES ............................................................... 73 LINE OUTPUT ............................................................................................................. 73 AC-COUPLED HEADPHONE OUTPUT....................................................................... 74 DC COUPLED (CAPLESS) HEADPHONE OUTPUT ................................................... 74 BTL LOUDSPEAKER OUTPUT ................................................................................... 75 COMBINED STEREO HEADSET / BTL EAR SPEAKER ............................................. 75 COMBINED HEADSET / SINGLE-ENDED EAR SPEAKER......................................... 75
PACKAGE DIMENSIONS ....................................................................................76 IMPORTANT NOTICE ..........................................................................................77
ADDRESS:................................................................................................................... 77
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WM9715L PIN CONFIGURATION
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ORDERING INFORMATION
DEVICE WM9715LGEFL/V WM9715LGEFL/RV Note: Reel quantity = 2,200 TEMP. RANGE -25 to +85oC -25 to +85oC PACKAGE 48-lead QFN (Pb-free) 48-lead QFN (Pb-free, tape and reel) MOISTURE LEVEL SENSITIVITY MSL3 MSL3 PEAK SOLDERING TEMP 260oC 260oC
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WM9715L
NAME DBVDD XTLIN XTLOUT DGND1 SDATAOUT BITCLK DGND2 SDATAIN DCVDD SYNC RESETB WIPER / AUX4 TPVDD X+/BR Y+/TR X-/TL Y-/BL TPGND PCBEEP PHONE MIC1 MIC2 LINEINL LINEINR AVDD AGND VREF MICBIAS COMP1 / AUX1 COMP2 / AUX2 BMON / AUX3 CAP2 MONOOUT SPKGND LOUT2 ROUT2 OUT3 SPKVDD HPOUTL HPGND HPOUTR AGND2 HPVDD DNC GENIRQ PENDOWN ADCIRQ SPDIF_OUT TYPE Supply Digital Input Digital Output Supply Digital Input Digital Output Supply Digital Output Supply Digital Input Digital Input Analogue Input Supply Analogue Input Analogue Input Analogue Input Analogue Input Supply Analogue Input Analogue Input Analogue Input Analogue Input Analogue Input Analogue Input Supply Supply Analogue Output Analogue Output Analogue Input Analogue Input Analogue Input Analogue In / Out Analogue Output Supply Analogue Output Analogue Output Analogue Output Supply Analogue Output Supply Analogue Output Supply Supply Do not connect Digital In / Out Digital Output Digital In / Out Digital In / Out Digital I/O Buffer Supply Clock Crystal Connection 1 / External Clock Input Clock Crystal Connection 2 Digital Ground (return path for both DCVDD and DBVDD) Serial Data Output from Controller / Input to WM9715L Serial Interface Clock Output to Controller Digital Ground (return path for both DCVDD and DBVDD) Serial Data Input to Controller / Output from WM9715L Digital Core Supply Serial Interface Synchronisation Pulse from Controller Reset (asynchronous, active Low, resets all registers to their default) Top Sheet Connection for 5-wire Touchpanels / Auxiliary ADC Input Touchpanel Driver Supply Touchpanel Connection: X+ (Right) for 4-wire / bottom right for 5-wire Touchpanel Connection: Y+ (Top) for 4-wire / top right for 5-wire Touchpanel Connection: X- (Left) for 4-wire / top left for 5-wire Touchpanel Connection: Y- (Bottom) for 4-wire / bottom left for 5-wire Touchpanel Driver Ground Line Input to analogue audio mixers, typically used for beeps Phone Input (RX) Left Microphone or Microphone 1 Input Right Microphone or Microphone 2 Input Left Line Input Right Line Input Analogue Supply (feeds audio DACs, ADCs, PGAs, mic boost, mixers) Analogue Ground Internal Reference Voltage (buffered CAP2) Bias Voltage for Microphones (buffered CAP2 x 1.8) Comparator 1 (dead battery alarm) / Auxiliary ADC Input 1 Comparator 2 (low battery alarm) / Auxiliary ADC Input 2 Battery Monitor Input / Auxiliary ADC Input 3 Internal Reference Voltage (normally AVDD/2, if not overdriven) Mono Output, intended for Phone TX signal Speaker Ground (feeds output buffers on pins 35 and 36) Left Output 2 (Speaker, Line or Headphone) Right Output 2 (Speaker, Line or Headphone) Analogue Output 3 (from AUXDAC or headphone pseudo-ground) Speaker Supply (feeds output buffers on pins 35 and 36) Headphone Left Output Headphone Ground (feeds output buffers on pins 37, 39, 41) Headphone Right Output Analogue Ground, Chip Substrate Headphone Supply (feeds output buffers on pins 37, 39, 41) Leave this pin unconnected General IRQ (Interrupt Request) Output Indicates that screen is being touched AUXADC "data ready" interrupt; also determines power up status. (See "Power Management" and "Applications" sections) SPDIF Digital Audio Output DESCRIPTION
PIN DESCRIPTION
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
Note: It is recommended that the QFN ground paddle should be connected to analogue ground on the application PCB.
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WM9715L ABSOLUTE MAXIMUM RATINGS
Production Data
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified. ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device. Wolfson tests its package types according to IPC/JEDEC J-STD-020B for Moisture Sensitivity to determine acceptable storage conditions prior to surface mount assembly. These levels are: MSL1 = unlimited floor life at <30C / 85% Relative Humidity. Not normally stored in moisture barrier bag. MSL2 = out of bag storage for 1 year at <30C / 60% Relative Humidity. Supplied in moisture barrier bag. MSL3 = out of bag storage for 168 hours at <30C / 60% Relative Humidity. Supplied in moisture barrier bag. The Moisture Sensitivity Level for each package type is specified in Ordering Information. CONDITION Digital supply voltages (DCVDD, DBVDD) Analogue supply voltages (AVDD, HPVDD, SPKVDD, TPVDD) Touchpanel supply voltage (TPVDD) Voltage range digital inputs Voltage range analogue inputs Voltage range touchpanel Inputs X+, X-, Y+ and YVoltage range touchpanel Inputs X+, X-, Y+ and YVoltage range, BMON/AUX3 (pin31) Operating temperature range, TA -25oC MIN -0.3V -0.3V AVDD -0.3V DGND -0.3V AGND -0.3V MAX +3.63V +3.63V AVDD +0.3V DBVDD +0.3V AVDD +0.3V TPVDD +0.3V AVDD +0.3V +5V +85oC
RECOMMENDED OPERATING CONDITIONS
PARAMETER Digital input/output buffer supply range Digital core supply range Analogue supply range Digital ground Analogue ground Difference AGND to DGND Notes: 1. 2. 3. 4. AVDD, DCVDD and DBVDD can all be different Digital supplies (DCVDD, DBVDD) must not exceed analogue supplies (AVDD, HPVDD, SPKVDD, TPVDD) by more than 0.3V AGND is normally the same as DGND DCVDD must be lower than or equal to DBVDD SYMBOL DBVDD DCVDD AVDD, HPVDD, SPKVDD, TPVDD DCGND, DBGND AGND, HPGND, SPKGND, TPGND Note 3 -0.3 TEST CONDITIONS Notes 1, 2 Notes 1, 2 MIN 1.8 1.8 1.8 0 0 0 +0.3 TYP MAX 3.6 or AVDD+0.3 3.6 or AVDD+0.3 3.6 UNIT V V V V V V
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WM9715L
ELECTRICAL CHARACTERISTICS
AUDIO OUTPUTS
Test Conditions DBVDD=3.3V, DCVDD = 3.3V, AVDD=HPVDD=SPKVDD =3.3V, TA = +25oC, 1kHz signal, fs = 48kHz, 18-bit audio data unless otherwise stated. PARAMETER Full-scale output Signal to Noise Ratio (A-weighted) Total Harmonic Distortion + Noise Power Supply Rejection SNR THD+N PSRR -3dB output 100mV, 20Hz to 20kHz signal on AVDD SYMBOL TEST CONDITIONS AVDD = 3.3V, PGA gains set to 0dB 85 MIN TYP 1 90 -86 50 -80 MAX UNIT V rms dB dB dB DAC to Line-Out (L/ROUT2 with 10k load)
Speaker Output (LOUT2/ROUT2 with 8 bridge tied load, INV=1) Output Power Output Power at 1% THD Abs. Max Output Power Total Harmonic Distortion Signal to Noise Ratio (A-weighted) Output Power per channel Total Harmonic Distortion (Note 1) PO PO POmax THD SNR PO=150mW 90 Output power is very closely correlated with THD; see below. 400 500 -65 0.05 97 mW mW dB % dB
Headphone Output (HPOUTL/R with 16 or 32 load) PO THD Output power is very closely correlated with THD; see below. PO=10mW, RL=16 PO=10mW, RL=32 PO=20mW, RL=16 PO=20mW, RL=32 Signal to Noise Ratio (A-weighted) Note: 1. All THD values are valid for the output power level quoted above - for example, at HPVDD=3.3V and RL=16, THD is -80dB when output power is 10mW. Higher output power is possible, but will result in deterioration in THD. SNR 90 -80 -81 -77 -79 95 dB -70 dB
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WM9715L
AUDIO INPUTS
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Test Conditions DBVDD=3.3V, DCVDD = 3.3V, AVDD = 3.3V, TA = +25oC, 1kHz signal, fs = 48kHz, 18-bit audio data unless otherwise stated. PARAMETER Full Scale Input Signal Level (for ADC 0dB Input at 0dB Gain) SYMBOL VINFS TEST CONDITIONS AVDD = 3.3V AVDD = 1.8V differential input mode (MS = 01) Input Resistance RIN PHONE, LINEINL/R pins PGA gain MIC1/2 pins PGA gain Input Capacitance Line input to ADC (LINEINL, LINEINR) Signal to Noise Ratio (A-weighted) Total Harmonic Distortion Power Supply Rejection Signal to Noise Ratio (A-weighted) Total Harmonic Distortion Power Supply Rejection Ratio SNR THD PSRR SNR THD PSRR -6dBFs 20Hz to 20kHz 80 88 -88 50 80 -80 50 -80 dB dB dB dB dB dB MIN TYP 1.0 0.545 half of the value listed above 10 6 17 12 5 22 18 pF k MAX UNIT V rms LINEINL/R, MICL/R and PHONE pins
Microphone input to 32 BTL ear speaker on OUT3/HPOUTL
AUXILIARY MONO DAC (AUXDAC)
Test Conditions AVDD = 3.3V, TA = +25oC, unless otherwise stated. PARAMETER Resolution Full scale output voltage Signal to Noise Ratio (A-weighted) Total Harmonic Distortion SNR THD AVDD=3.3V 65 SYMBOL TEST CONDITIONS MIN TYP 12 1 70 -63 -50 MAX UNIT bits Vrms dB dB
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WM9715L
TOUCHPANEL AND AUXILIARY ADC
Test Conditions DBVDD=3.3V, DCVDD = 3.3V, AVDD = TPVDD = 3.3V, TA = +25oC, MCLK = 24.576 MHz, unless otherwise stated. PARAMETER Input Voltage Input leakage current ADC Resolution Differential Non-Linearity Error Integral Non-Linearity Error Offset Error Gain Error Power Supply Rejection Switch matrix resistance Programmable Pull-up resistor Pen down detector threshold Pressure measurement current BMON/AUX3 (pin 31 only) Input Range Scaling Input Resistance (Note 1) during measurement average over time AVDD = 3.3V AVDD = 1.8V AGND AGND -3% 1/3 30 30 / duty cycle 5 3.3 +3% k V V IP PIL = 1 PIL = 0 RPU RPU = 000001 63 PSRR DNL INL 4 8 50 10 68 VDD/2 400 200 73 -0.99 AUX pin not selected as AUX ADC input SYMBOL TEST CONDITIONS MIN AGND <10 12 0.15 +1.75 3 TYP MAX AVDD UNIT V nA bits LSB LSB LSB LSB dB k V A Input Pins X+, X-, Y+, Y-, WIPER/AUX4, COMP1/AUX1, COMP2/AUX2 and BMON/AUX3
Note: 1. Current only flows into pin 31 during a measurement. At all other times, BMON/AUX3 is effectively an open circuit.
COMPARATORS
Test Conditions AVDD = 3.3V, TA = +25oC, unless otherwise stated. PARAMETER Input Voltage Input leakage current Comparator Input Offset (COMP1, COMP2 only) COMP2 delay (COMP2 only) 24.576MHz crystal pin not selected as AUX ADC input -50 0 SYMBOL TEST CONDITIONS MIN AGND <10 +50 10.9 TYP MAX AVDD UNIT V nA mV s COMP1/AUX1 and COMP2/AUX2 (pins 29, 30)
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WM9715L
REFERENCE VOLTAGES
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Test Conditions DBVDD=3.3V, DCVDD = 3.3V, AVDD = 3.3V, TA = +25oC, 1kHz signal, fs = 48kHz, 18-bit audio data unless otherwise stated. PARAMETER Audio ADCs, DACs, Mixers Reference Input/Output Buffered Reference Output Microphone Bias Bias Voltage Bias Current Source Output Noise Voltage VMICBIAS IMICBIAS Vn 1K to 20kHz 15 2.88 2.97 3.06 3 V mA nV/Hz CAP2 pin VREF pin 1.6 1.6 1.65 1.65 1.7 1.7 V V SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
DIGITAL INTERFACE CHARACTERISTICS
Test Conditions o DBVDD = 3.3V, DCVDD = 3.3V, TA = +25 C, unless otherwise stated. PARAMETER Input HIGH level Input LOW level Output HIGH level Output LOW level Clock Frequency Master clock (XTLIN pin) AC'97 bit clock (BIT_CLK pin) AC'97 sync pulse (SYNC pin) Note: 1. 2. All audio and non-audio sample rates and other timing scales proportionately with the master clock. For signal timing on the AC-Link, please refer to the AC'97 specification (Revision 2.2) 24.576 12.288 48 MHz MHz kHz SYMBOL VIH VIL VOH VOL source current = 2mA sink current = 2mA DBVDDx0.9 DBVDDx0.1 TEST CONDITIONS MIN DBVDDx0.7 DBVDDx0.3 TYP MAX UNIT V V Digital Logic Levels (all digital input or output pins) - CMOS Levels
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WM9715L
HEADPHONE / SPEAKER OUTPUT THD VERSUS POWER
-20 Headphone Power vs THD+N (32Ohm load)
-40
THD+N (dB)
-60
-80
-100 0 5 10 15 Power (mW) 20 25 30
-20 Headphone Power vs THD+N (16Ohm load)
-40
THD+N (dB)
-60
-80
-100 0 10 20 30 Power (mW) 40 50 60
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WM9715L
POWER CONSUMPTION
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The power consumption of the WM9715L depends on the following factors. * Supply voltages: Reducing the supply voltages also reduces digital supply currents, and therefore results in significant power savings especially in the digital sections of the WM9715L. * Operating mode: Significant power savings can be achieved by always disabling parts of the WM9715L that are not used (e.g. audio ADC, DAC, touchpanel digitiser).
26h 14:8 24h 15:0 Other Settings V 3.3 2.5 1.8 3.3 2.5 1.8 3.3 2.5 1.8 3.3 2.5 1.8 3.3 2.5 1.8 3.3 2.5 1.8 3.3 2.5 1.8 3.3 2.5 1.8 3.3 2.5 1.8 3.3 2.5 1.8 3.3 2.5 1.8 3.3 2.5 1.8 3.3 2.5 1.8 3.3 2.5 1.8 AVDD I (mA) 0.0005 0.0004 0.0003 0.005 0.004 0.003 0.56 0.37 0.241 1.1 0.76 0.508 0.05 0.02 0.009 0.08 0.04 0.027 2.36 1.838 1.218 2.385 1.837 1.218 3.27 2.66 1.838 9.461 7.46 5.318 3.45 2.549 1.738 3.62 2.71 1.748 3.62 2.71 1.748 9.593 7.37 5.388 DCVDD I (mA) 0 0 0 0 0 0 0 0 0 0 0 0 1.301 0.883 0.571 5.85 3.922 2.87 0 0 0 0 0 0 11.21 7.78 5.21 12.22 8.552 5.799 9.884 6.755 4.606 9.8 6.78 4.606 9.8 6.78 4.606 12.26 8.563 5.8 DBVDD I (mA) 0 0 0 0 0 0 0 0 0 0 0 0 3.26 2.1 1.41 2.67 2.1 1.41 0 0 0 0 0 0 2.6 2.13 1.41 2.62 2.1 1.48 2.6 2.1 1.41 2.6 2.1 1.47 2.6 2.1 1.41 2.62 2.12 1.48 Total Power (mW) 0.00165 0.001 0.00054 0.0165 0.01 0.0054 1.848 0.925 0.4338 3.63 1.9 0.9144 15.2163 7.5075 3.582 28.38 15.155 7.7526 7.788 4.595 2.1924 7.8705 4.5925 2.1924 56.364 31.425 15.2244 80.1933 45.28 22.6746 52.5822 28.51 13.9572 52.866 28.975 14.0832 52.866 28.975 13.9752 80.7609 45.1325 22.8024
Mode Description OFF (lowest possible power) Clocks stopped LPS (Low Power Standby) VREF maintained using 1MOhm string Standby Mode (ready to playback) VREF maintained using 50kOhm string "Idle" Mode VREF maintained using 50kOhm string use LPS mode instead, if possible Touchpanel only (waiting for pen-down) AC-Link running Touchpanel only (continuous conversion) 93.75 points per second Phone Call - using headphone / ear speaker HPOUTL, HPOUTR and OUT3 active AC-Link stopped Phone Call - using loudspeaker AC-Link stopped Record from mono microphone with MICBIAS all analogue outputs disabled Record phone call both sides mixed to mono call using headphone / ear speaker DAC Playback - using loudspeaker
1111111 0111111111111111 58h, SVD = 1
1111111 0111111111111111
1110111 0111111111111111
1100111 0111111111111111
1101111 0111111111111111 76h = 0C00h 78h = 0001h 1001111 0111111111111111 76h = 0C00h 78h = C001h 0110011 0111100010101100 0Eh, bit 7 = 1 (mic gain boost) 1110011 0111101100110100 0Eh, bit 7 = 1 (mic gain boost) 1000110 0110101111111111 0Eh, bit 7 = 1 (mic gain boost) 0000000 0000000010001000 0Eh, bit 7 = 1 (mic gain boost) 1000001 0001111101110111
DAC Playback - using headphone
0000001 0001110011101111
DAC Playback - to Line-out
0000001 0001110011110111
Maximum Power (everything on)
0000000 0000000000000000 0Eh, bit 7 = 1 (mic gain boost)
V 3.3 2.5 1.8 3.3 2.5 1.8 3.3 2.5 1.8 3.3 2.5 1.8 3.3 2.5 1.8 3.3 2.5 1.8 3.3 2.5 1.8 3.3 2.5 1.8 3.3 2.5 1.8 3.3 2.5 1.8 3.3 2.5 1.8 3.3 2.5 1.8 3.3 2.5 1.8 3.3 2.5 1.8
V 3.3 2.5 1.8 3.3 2.5 1.8 3.3 2.5 1.8 3.3 2.5 1.8 3.3 2.5 1.8 3.3 2.5 1.8 3.3 2.5 1.8 3.3 2.5 1.8 3.3 2.5 1.8 3.3 2.5 1.8 3.3 2.5 1.8 3.3 2.5 1.8 3.3 2.5 1.8 3.3 2.5 1.8
Table 1 Supply Current Consumption Notes: 1. 2. All figures are at TA = +25oC, audio sample rate fs = 48kHz, with zero signal (quiescent). The power dissipated in the headphone, speaker and touchpanel is not included in the above table.
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WM9715L
DEVICE DESCRIPTION
INTRODUCTION
The WM9715L is designed to meet the mixed-signal requirements of portable and wireless computer systems. It includes audio recording and playback, touchpanel digitisation, battery monitoring, auxiliary ADC and interrupt functions, all controlled through a single 5-wire AC-Link interface.
SOFTWARE SUPPORT
The basic audio features of the WM9715L are software compatible with standard AC'97 device drivers. However, to better support the touchpanel and other additional functions, Wolfson Microelectronics supplies custom device drivers for selected CPUs and operating systems. Please contact your local Wolfson Sales Office for more information.
AC'97 COMPATIBILITY
The WM9715L uses an AC'97 interface to communicate with a microprocessor or controller. The audio functions are largely compliant with AC'97 Revision 2.2. The following differences from the AC'97 standard are noted: * Pinout: The function of some pins has been changed to support device specific features. The PHONE and PCBEEP pins have been moved to different locations on the device package. Package: The default package for the WM9715L is a 7x7mm leadless QFN package. Audio mixing: The WM9715L handles all the audio functions of a smartphone, including audio playback, voice recording, phone calls, phone call recording, ring tones, as well as simultaneous use of these features. The AC'97 mixer architecture does not fully support this. The WM9715L therefore uses a modified AC'97 mixer architecture with three separate mixers. Tone Control, Bass Boost and 3D Enhancement: These functions are implemented in the digital domain and therefore affect only signals being played through the audio DACs, not all output signals as stipulated in AC'97.
*
*
Some other functions are additional to AC'97: * * * * * * * On-chip BTL loudspeaker driver On-chip BTL driver for ear speaker (phone receiver) Auxiliary mono DAC for ring tones, system alerts etc. Touchpanel controller Auxiliary ADC Inputs 2 Analogue Comparators for Battery Alarm Programmable Filter Characteristics for Tone Control and 3D Enhancement
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WM9715L
AUDIO PATHS OVERVIEW
Production Data
L
LINEINL Pin 23
20h:7 (Loopback) ADC Left AC Link 1 0 Slot 3 Tone and 3D 08h / 22h / 20h:13 (3DE)
18h:12-8 00000 = +12dB 11111 = -34.5dB
Left Channel 18 Bit DAC
PCM PGA
to SPKR MIXER
18 h 10 :15 h: 1 0C 5 h:1 5 0Ah :15-1 2 14h:15-12
L Line Volume 02h:12-8 00000 = 0dB 11111 = -46.5dB 1 headphone mixer L 0 02h:6 (INV) Zerocross detect 02h:7 (ZC) 02h:15 (MUTE)
LOUT2 Pin 35
10h:12-8 00000 = +12dB 11111 = -34.5dB LINEL PGA to SPKR MIXER
6dB -> -15dB
6dB -> -15dB
6dB -> -15dB
6dB -> -15dB
6dB -> -15dB
-12 14h:15 1-7 h:1 7 14 1h:1 12 14 51 h: 12
1 0 16h:8 (SRC)
PCBEEP Pin 19
0Ch:0-4 00000 = +12dB 11111 = -34.5dB
6dB -> -15dB
L Headphone Volume 04h:12-8 00000 = 0dB 11111 = -46.5dB
HPOUTL Pin 39
Zerocross detect 04h:7 (ZC) 04h:15 (MUTE) Phone Mixer
PHONE Pin 20
PHONE PGA
10 h 10 :13 h: 1 18 3 h:1 3 18h :13
6dB -> -15dB
0Eh:12-8 00000 = +12dB 11111 = -34.5dB
0Ah7:4
14+7 0Eh: 7 3+ h:1 1 0E 1 3:1 Ah 1
0dB / 20dB
MIC1 Pin 21
MICL PGA OEh:6-5 (MS)
0dB / 20dB
Mono Volume 06h:4-0 00000 = 0dB 11111 = -46.5dB
1 1 2 Ah : h:7 13 -4 -11
0dB / 20dB
MONOOUT Pin 33
Zerocross detect 06h:7 (ZC) 06h:15 (MUTE)
0dB / 20dB
6dB -> -15dB
PCBEEP
1Ah[10:8] = 110 Note: MS bits also affect sidetone path 1Ah[10:8] = 101 Gain Ranges: 1Ch:13 (GRL=0) 1Ch:11:8 0000 = 0db 1111 = +22.5dB 1Ch:6 (GRL=1) 1Ch:13-8 11111 = +30dB 00000 = -17.25dB ADC PGA 1Ch:15 (Mute)
PHONE DACR LINER MICR MICL ALCL ALCR AUXDAC MONOMIX SPKRMIX
OUT3 Volume 16h:4-0 00000 = 0dB 11111 = -46.5dB
(1Ah[10:8] = 000) & (MS = 01) (1Ah[10:8] = 000) & (MS = 00 or 11) 1Ah[10:8] = 111 1Ah[10:8] = 100 (1Ah[10:8] = 000) & (MS = 10) 1Ah[10:8] = 011 1Ah: 10-8
1Ah:14 0 = 0dB 1 = 20dB
Left Channel 18 Bit ADC Variable Slot 5C:1-0 (ASS) 5C:3 (HPF) 5C:4 (ADCO) ALC:5Ch/60h/62h
16h:10-9 (OUT3SRC)
Zero- Pin cross detect
OUT3 37
AC Link
16h:7 (ZC) 16h:15 (MUTE)
AUXDAC ALCR ALCL MICL MICR LINER DACR
R
LINEINR Pin 24
20h:7 (Loopback) ADC Right AC Link 1 0 Slot 4 Tone and 3D 08h / 22h / 20h:13 (3DE)
18h:4-0 00000 = +12dB 11111 = -34.5dB
PHONE PCBEEP MONOMIX SPKRMIX
Right Channel 18 Bit DAC
PCM PGA
10h:5-0 00000 = +12dB 11111 = -34.5dB LINER PGA
12 Bit Resistor string DAC 2Eh/64h/12h:0(EN)
5Ch:8 (DS) 0Eh:5-0 00000 = +12dB 11111 = -34.5dB MS = 01 MICR PGA MS = 10 or 11 0Eh:6-5 (MS) Note: MS bits also affect ADC input path from MICs
6dB -> -15dB
6dB -> -15dB
18 h 10 :15 h: 1 0C 5 h:1 5 0Ah :15-1 2
headphone mixer R
R Headphone Volume 04h:4-0 00000 = 0dB 11111 = -46.5dB
14h:15-12
-12 14h:15 1-8 h:1 8 14 11 h: 12 1 4 51 h: 12
6dB -> -15dB
HPOUTR Pin 41
Zerocross detect 04h:7 (ZC) 04h:15 (MUTE)
6dB -> -15dB
6dB -> -15dB
MIC2 Pin 22
6dB -> -15dB
FROM LINEL PGA
10 h: 10 14 h1 4 18 h:1 4 18h :14
R Line Volume 02h:4-0 00000 = 0dB 11111 = -46.5dB 16h:8 (SRC) Speaker Mixer 1 0 Zerocross detect 02h:7 (ZC) 02h:15 (MUTE)
ROUT2 Pin 36
FROM DACL
0Ch:14
6dB -> -15dB
1Ah[2:0] = 110 Note: MS bits also affect 1Ah[2:0] = 101 sidetone path (1Ah[2:0] = 000) & (MS = 01) (1Ah[2:0] = 000) & (MS = 10 or 11) (1Ah[2:0] = 000) & (MS = 00) 1Ah[2:0] = 111 1Ah[2:0] = 100 1Ah[2:0] = 011 ADC PGA 1Ch:15 (Mute) 1Ah: 2-0
6dB -> -15dB
11-8 0Ah: -8 :11 12h
Gain Ranges: 1Ch:6 (GRR=0) 1Ch:3:0 0000 = 0db 1111 = +22.5dB 1Ch:6 (GRR=1) 1Ch:5-0 11111 = +30dB 00000 = -17.25dB
PR3 (REF disable) & 58h:10 (SVD) 1Ah:14 0 = 0dB 1 = 20dB 4.5k Right Channel 18 Bit ADC Variable Slot 5C:1-0 (ASS) 5C:3 (HPF) 5C:4 (ADCO) ALC:5Ch/60h/62h 3.6k
MICBIAS Pin 28
AC Link
500k
50k
500k
50k
AVDD Pin 25
AGND Pin 24
CAP2 Pin 32
VREF Pin 27
Figure 1 Audio Paths Overview
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AUDIO INPUTS
The following sections give an overview of the analogue audio input pins and their function. For more information on recommended external components, please refer to the "Applications Information" section.
LINE INPUT
The LINEINL and LINEINR inputs are designed to record line level signals, and/or to mix into one of the analogue outputs. Both pins are directly connected to the record selector. The record PGA adjusts the recording volume, controlled by register 1Ch or by the ALC function. For analogue mixing, the line input signals pass through a separate PGA, controlled by register 10h. The signals can be routed into all three output mixers (headphone, speaker and phone). Each LINEIN-to-mixer path has an independent mute bit. When the line inputs are not used, the line-in PGA can be switched off to save power (see "Power Management" section). LINEINL and LINEINR are biased internally to the reference voltage VREF. Whenever the inputs are muted or the device placed into standby mode, the inputs remain biased to VREF using special antithump circuitry to suppress any audible clicks when changing inputs. REGISTER ADDRESS 10h BIT 12:8 LABEL LINEINL VOL DEFAULT 01000 (0dB) DESCRIPTION LINEINL input gain 00000: +12dB ... (1.5dB steps) 11111: -34.5dB LINEINR input gain similar to LINEINLVOL Mute LINEIN path to headphone mixer 1: Mute, 0: No mute (ON) Mute LINEIN path to speaker mixer 1: Mute, 0: No mute (ON) Mute LINEIN path to phone mixer 1: Mute, 0: No mute (ON)
4:0 15 14 13
LINEINR VOL L2H L2S L2P
01000 (0dB) 1 1 1
Table 2 Line Input Control
MICROPHONE INPUT
The MIC1 and MIC2 inputs are designed for direct connection to single-ended mono, stereo or differential mono microphone. If the microphone is mono, the same signal appears on both left and right channels. In stereo mode, MIC1 is routed to the left and MIC2 to the right channel. For voice recording, the microphone signal is directly connected to the record selector. The record PGA adjusts the recording volume, controlled by register 1Ch or by the ALC function. For analogue mixing, the signal passes through a separate PGA, controlled by register 0Eh. The microphone signal can be routed into the phone mixer (for normal phone call operation) and/or the headphone mixer (using register 14h, see "Audio Mixers / Sidetone Control" section), but not into the speaker mixer (to prevent acoustic feedback from the speaker into the microphone). When the microphone inputs are not used, the microphone PGA can be switched off to save power (see "Power Management" section). MIC1 and MIC2 are biased internally to the reference voltage VREF. Whenever the inputs are muted or the device placed into standby mode, the inputs remain biased to VREF using special anti-thump circuitry to suppress any audible clicks when changing inputs.
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Production Data It is also possible to use the LINEINL and LINEINR pins as a second differential microphone input. This is achieved by setting the DS bit (register 5Ch, bit 11) to `1'. This disables the line-in audio paths and routes the signal from LINEINL and LINEINR through the differential mic path, as if it came from the MIC1 and MIC2 pins. Only one differential microphone be used at a time. The DS bit only has an effect when MS = 01 (differential mode). REGISTER ADDRESS 0Eh Mic Volume BIT 14 13 12:8 LABEL M12P M22P LMICVOL DEFAULT 1 1 01000 (0dB) 0 DESCRIPTION Mute MIC1 path to phone mixer 1: Mute, 0: No mute (ON) Mute MIC2 path to phone mixer 1: Mute, 0: No mute (ON) Left microphone volume Only used when MS = 11 Similar to MICVOL Microphone gain boost (Note 1) 1: 20dB boost ON 0: No boost (0dB gain) Microphone mode select 00 Single-ended mono (left) left = right = MIC1 (pin 21) Volume controlled by MICVOL Differential mono mode left = right = MIC1 - MIC2 Volume controlled by MICVOL Single-ended mono (right) left = right = MIC2 (pin 22) Volume controlled by MICVOL Stereo mode MIC1 = left, MIC2 = right Left Volume controlled by LMICVOL Right volume controlled by MICVOL
7
20dB
6:5
MS
00
01
10
11
4:0
MICVOL
01000 (0dB)
Microphone volume to mixers 00000: +12dB ... (1.5dB steps) 11111: -34.5dB Differential Microphone Select 0 : Use MIC1 and MIC2 1: Use LINEL and LINER (Note 2)
5Ch Additional Analogue Functions
8
DS
0
Table 3 Microphone Input Control Note: 1. 2. The 20dB gain boost acts on the input to the phone mixer only. A separate microphone boost for recording can be enabled using the BOOST bit in register 1Ah. When the LINEL and LINER are selected for differential microphone select then the MIC1 and MIC2 input pins become disabled, these signals can therefore not be routed internally to the device.
MICROPHONE BIAS
The MICBIAS output (pin 28) provides a low noise reference voltage suitable for biasing electret type microphones and the associated external resistor biasing network. The internal MICBIAS circuitry is shown below. Note that the maximum source current capability for MICBIAS is 3mA. The external biasing resistors and microphone cartridge therefore must limit the MICBIAS current to 3mA.
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Figure 2 Microphone Bias Schematic
PHONE INPUT
Pin 20 (PHONE) is a mono, line level input designed to connect to the receive path of a telephony device. The pin connects directly to the record selector for phone call recording (Note: to record both sides of a phone call, one ADC channel should record the PHONE signal while the other channel records the MIC signal). The RECVOL PGA adjusts the recording volume, controlled by register 1Ch or by the ALC function. To listen to the PHONE signal, the signal passes through a separate PGA, controlled by register 0Ch. The signal can be routed into the headphone mixer (for normal phone call operation) and/or the speaker mixer (for speakerphone operation), but not into the phone mixer (to prevent forming a feedback loop). When the phone input is not used, the phone-in PGA can be switched off to save power (see "Power Management" section). PHONE is biased internally to the reference voltage VREF. Whenever the input is muted or the device placed into standby mode, the input remains biased to VREF using special anti-thump circuitry to suppress any audible clicks when changing inputs. REGISTER ADDRESS 0Ch Phone Input BIT 15 14 4:0 LABEL P2H P2S PHONE VOL DEFAULT 1 1 01000 (0dB) DESCRIPTION Mute PHONE path to headphone mixer 1: Mute, 0: No mute (ON) Mute PHONE path to speaker mixer 1: Mute, 0: No mute (ON) PHONE input gain 00000: +12dB ... (1.5dB steps) 11111: -34.5dB
Table 4 Phone Input Control
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PCBEEP INPUT
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Pin 19 (PCBEEP) is a mono, line level input intended for externally generated signal or warning tones. It is routed directly to the record selector and all three output mixers, without an input amplifier. The signal gain into each mixer can be independently controlled, with a separate mute bit for each signal path. REGISTER ADDRESS 0Ah PCBEEP input BIT 15 14:12 LABEL B2H B2HVOL DEFAULT 1 010 (0dB) DESCRIPTION Mute PCBEEP path to headphone mixer 1: Mute, 0: No mute (ON) PCBEEP to headphone mixer gain 000: +6dB ... (3dB steps) 111: -15dB Mute PCBEEP path to speaker mixer 1: Mute, 0: No mute (ON) PCBEEP to speaker mixer gain 000: +6dB ... (3dB steps) 111: -15dB Mute PCBEEP path to phone mixer 1: Mute, 0: No mute (ON) PCBEEP to phone mixer gain 000: +6dB ... (3dB steps) 111: -15dB
11 10:8
B2S B2SVOL
1 010 (0dB)
7 6:4
B2P B2PVOL
1 010 (0dB)
Table 5 PCBEEP Control
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AUDIO ADC
The WM9715L has a stereo sigma-delta ADC to digitize audio signals. The ADC achieves high quality audio recording at low power consumption. The ADC sample rate can be controlled by writing to a control register (see "Variable Rate Audio"). It is independent of the DAC sample rate. To save power, the left and right ADCs can be separately switched off using the PD11 and PD12 bits, whereas PR0 disables both ADCs (see "Power Management" section). If only one ADC is running, the same ADC data appears on both the left and right AC-Link slots.
HIGH PASS FILTER
The WM9715L audio ADC incorporates a digital high-pass filter that eliminates any DC bias from the ADC output data. The filter is enabled by default. For DC measurements, it can be disabled by writing a `1' to the HPF bit (register 5Ch, bit 3).
ADC SLOT MAPPING
By default, the output of the left audio ADC appears on slot 3 of the SDATAIN signal (pin 8), and the right ADC data appears on slot 4. However, the ADC output data can also be sent to other slots, by setting the ASS (ADC slot select) control bits as shown below. REGISTER ADDRESS 5Ch Additional Function Control BIT 1:0 LABEL ASS DEFAULT 00 DESCRIPTION ADC to slot mapping 00: Left = Slot 3, Right = Slot 4 (default) 01: Left = Slot 7, Right = Slot 8 10: Left = Slot 6, Right = Slot 9 11: Left = Slot 10, Right = Slot 11 High-pass filter disable 0: Filter enabled (for audio) 1: Filter disabled (for DC measurements)
3
HPF
0
Table 6 ADC Control
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RECORD SELECTOR
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The record selector determines which input signals are routed into the audio ADC. The left and right channels can be selected independently. This is useful for recording a phone call: one channel can be used for the RX signal and the other for the TX signal, so that both sides of the conversation are digitized. REGISTER ADDRESS 1Ah Record Select BIT 14 LABEL BOOST DEFAULT 0 DESCRIPTION 20dB Boost 1: Boost ADC input signal by 20dB 0 :No boost Record to phone path enable 00: Left ADC and Right ADC to phone mixer 01 : Left ADC to phone mixer 10: Right ADC to phone imixer 11 : Muted 20dB Boost for ADC to phone signal 1: Boost signal by 20dB 0 :No boost Left ADC signal source 000: MIC* (pre-PGA) 001-010: Reserved (do not use this setting) 011: Speaker mix 100: LINEINL (pre-PGA) 101: Headphone Mix (left) 110: Phone Mix 111: PHONE (pre-PGA) Right ADC signal source 000: MIC* (pre-PGA) 001-010: Reserved (do not use this setting) 011: Speaker mix 100: LINEINR (pre-PGA) 101: Headphone Mix (right) 110: Phone Mix 111: PHONE (pre-PGA)
13:12
R2P
11
11
R2PBOOST
0
10:8
RECSL
000
2:0
RECSR
000
Table 7 Audio Record Selector Note: *In stereo mic mode, MIC1 is routed to the left ADC and MIC2 to the right ADC. In all mono mic modes, the same signal (MIC1, MIC2 or MIC1-MIC2) is routed to both the left and right ADCs. See "Microphone Input" section for details.
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The amplitude of the signal that enters the audio ADC is controlled by the Record PGA (Programmable Gain Amplifier). The PGA gain can be programmed either by writing to the Record Gain register, or by the Automatic Level Control (ALC) circuit (see next section). When the ALC is enabled, any writes to the Record Gain register have no effect. Two different gain ranges can be implemented: the standard gain range defined in the AC'97 standard, or an extended gain range with smaller gain steps. The ALC circuit always uses the extended gain range, as this has been found to result in better sound quality. The output of the Record PGA can also be mixed into the phone and/or headphone outputs (see "Audio Mixers"). This makes it possible to use the ALC function for the microphone signal in a smartphone application. REGISTER ADDRESS 1Ch Record Gain BIT 15 LABEL RMU DEFAULT 1 DESCRIPTION Mute Audio ADC (both channels) 1: Mute (OFF) 0: No Mute (ON) Gain range select (left) 0: Standard (0 to 22.5dB, 1.5dB step size) 1: Extended (-17.25 to +30dB, 0.75dB steps) Record Volume (left) Standard (GRL=0) XX0000: 0dB XX0001: +1.5dB ... (1.5dB steps) XX1111: +22.5dB 7 ZC 0 Extended (GRL=1) 000000: -17.25dB 000001: -16.5dB ... (0.75dB steps) 111111: +30dB
RECORD GAIN
14
GRL
0
13:8
RECVOLL
000000
Zero Cross Enable 0: Record Gain changes immediately 1: Record Gain changes when signal is zero or after time-out Gain range select (right) Similar to GRL Record Volume (right) Similar to RECVOLL
6 5:0
GRR RECVOLR
0 000000
Table 8 Record Gain Register
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AUTOMATIC LEVEL CONTROL
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The WM9715L has an automatic level control that aims to keep a constant recording volume irrespective of the input signal level. This is achieved by continuously adjusting the PGA gain so that the signal level at the ADC input remains constant. A digital peak detector monitors the ADC output and changes the PGA gain if necessary.
input signal
PGA gain
signal after ALC
ALC target level
hold time
decay time
attack time
Figure 3 ALC Operation The ALC function is enabled using the ALCSEL control bits. When enabled, the recording volume can be programmed between -6dB and -28.5dB (relative to ADC full scale) using the ALCL register bits. HLD, DCY and ATK control the hold, decay and attack times, respectively: Hold time is the time delay between the peak level detected being below target and the PGA gain beginning to ramp up. It can be programmed in power-of-two (2n) steps, e.g. 2.67ms, 5.33ms, 10.67ms etc. up to 43.7s. Alternatively, the hold time can also be set to zero. The hold time only applies to gain ramp-up, there is no delay before ramping the gain down when the signal level is above target. Decay (Gain Ramp-Up) Time is the time that it takes for the PGA gain to ramp up across 90% of its range (e.g. from -15B up to 27.75dB). The time it takes for the recording level to return to its target value therefore depends on both the decay time and on the gain adjustment required. If the gain adjustment is small, it will be shorter than the decay time. The decay time can be programmed in power-of-two (2n) steps, from 24ms, 48ms, 96ms, etc. to 24.58s. Attack (Gain Ramp-Down) Time is the time that it takes for the PGA gain to ramp down across 90% of its range (e.g. from 27.75dB down to -15B gain). The time it takes for the recording level to return to its target value therefore depends on both the attack time and on the gain adjustment required. If the gain adjustment is small, it will be shorter than the attack time. The attack time can be programmed in power-of-two (2 ) steps, from 6ms, 12ms, 24ms, etc. to 6.14s. When operating in stereo, the peak detector takes the maximum of left and right channel peak values, and any new gain setting is applied to both left and right PGAs, so that the stereo image is preserved. However, the ALC function can also be enabled on one channel only. In this case, only one PGA is controlled by the ALC mechanism, while the other channel runs independently with its PGA gain set through the control register.
n
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REGISTER ADDRESS 62h ALC / Noise Gate Control BIT 15:14 LABEL ALCSEL DEFAULT 00 (OFF) DESCRIPTION ALC function select 00 = ALC off (PGA gain set by register) 01 = Right channel only 10 = Left channel only 11 = Stereo (PGA registers unused) Note: Ensure that RECVOLL and RECVOLR settings (reg. 1Ch) are the same before entering this mode PGA gain limit for ALC 111 = +30dB 110 = +24dB ....(6dB steps) 001 = -6dB 000 = -12dB ALC Zero Cross enable (overrides ZC bit in register 1Ch) 0: PGA Gain changes immediately 1: PGA Gain changes when signal is zero or after time-out Programmable zero cross timeout 11 217 x MCLK period 16 10 2 x MCLK period 01 215 x MCLK period 00 214 x MCLK period ALC target - sets signal level at ADC input 0000 = -28.5dB FS 0001 = -27.0dB FS ... (1.5dB steps) 1110 = -7.5dB FS 1111 = -6dB FS ALC hold time before gain is increased. 0000 = 0ms 0001 = 2.67ms 0010 = 5.33ms ... (time doubles with every step) 1111 = 43.691s ALC decay (gain ramp-up) time 0000 = 24ms 0001 = 48ms 0010 = 96ms ... (time doubles with every step) 1010 or higher = 24.58s ALC attack (gain ramp-down) time 0000 = 6ms 0001 = 12ms 0010 = 24ms ... (time doubles with every step) 1010 or higher = 6.14s
13:11
MAXGAIN
111 (+30dB)
8
ALCZC
0
9:10
ZC TIMEOUT
11
60h ALC Control
15:12
ALCL
1011 (-12dB)
11:8
HLD
0000 (0ms)
7:4
DCY
0011 (192ms)
3:0
ATK
0010 (24ms)
Table 9 ALC Control
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MAXIMUM GAIN
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The MAXGAIN register sets the maximum gain value that the PGA can be set to whilst under the control of the ALC. This has no effect on the PGA when ALC is not enabled.
PEAK LIMITER
To prevent clipping when a large signal occurs just after a period of quiet, the ALC circuit includes a limiter function. If the ADC input signal exceeds 87.5% of full scale (-1.16dB), the PGA gain is ramped down at the maximum attack rate (as when ATK = 0000), until the signal level falls below 87.5% of full scale. This function is automatically enabled whenever the ALC is enabled. (Note: If ATK = 0000, then the limiter makes no difference to the operation of the ALC. It is designed to prevent clipping when long attack times are used).
NOISE GATE
When the signal is very quiet and consists mainly of noise, the ALC function may cause "noise pumping", i.e. loud hissing noise during silence periods. The WM9715L has a noise gate function that prevents noise pumping by comparing the signal level at the input pins (i.e. before the record PGA) against a noise gate threshold, NGTH. Provided that the noise gate function is enabled (NGAT = 1), the noise gate cuts in when: * Signal level at ADC [dB] < NGTH [dB] + PGA gain [dB] + Mic Boost gain [dB]
This is equivalent to: * Signal level at input pin [dB] < NGTH [dB]
The PGA gain is then held constant (preventing it from ramping up as it normally would when the signal is quiet). If the NGG bit is set, the ADC output is also muted when the noise gate cuts in. The table below summarises the noise gate control register. The NGTH control bits set the noise gate threshold with respect to the ADC full-scale range. The threshold is adjusted in 1.5dB steps. Levels at the extremes of the range may cause inappropriate operation, so care should be taken with set-up of the function. Note that the noise gate only works in conjunction with the ALC function, and always operates on the same channel(s) as the ALC (left, right, both, or none). REGISTER ADDRESS 62h ALC / Noise Gate Control 7 BIT LABEL NGAT DEFAULT 0 DESCRIPTION Noise gate function enable 1 = enable 0 = disable Noise gate type 0 = PGA gain held constant 1 = mute ADC output Noise gate threshold 00000: -76.5dBFS 00001: -75dBFS ... 1.5 dB steps 11110: -31.5dBFS 11111: -30dBFS
5
NGG
0
4:0
NGTH(4:0)
00000
Table 10 Noise Gate Control
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AUDIO DACS
STEREO DAC
The WM9715L has a stereo sigma-delta DAC that achieves high quality audio playback at low power consumption. Digital tone control, adaptive bass boost and 3-D enhancement functions operate on the digital audio data before it is passed to the stereo DAC. (Contrary to the AC'97 specification, they have no effect on analogue input signals or signals played through the auxiliary DAC. Nevertheless, the ID2 and ID5 bits in the reset register, 00h, are set to `1' to indicate that the WM9715L supports tone control and bass boost.) The DAC output has a PGA for volume control. The DAC sample rate can be controlled by writing to a control register (see "Variable Rate Audio"). It is independent of the ADC sample rate. The left and right DACs can be separately powered down using the PD13 and PD14 control bits, whereas the PR1 bit disables both DACs (see "Power Management" section).
STEREO DAC VOLUME
The volume of the DAC output signal is controlled by a PGA (Programmable Gain Amplifier). It can be mixed into the headphone, speaker and phone output paths (see "Audio Mixers"). REGISTER ADDRESS 18h DAC Volume BIT 15 14 13 12:8 LABEL D2H D2S D2P DACL VOL DEFAULT 1 1 1 01000 (0dB) DESCRIPTION Mute DAC path to headphone mixer 1: Mute, 0: No mute (ON) Mute DAC path to speaker mixer 1: Mute, 0: No mute (ON) Mute DAC path to phone mixer 1: Mute, 0: No mute (ON) Left DAC Volume 00000: +12dB ... (1.5dB steps) 11111: -34.5dB Right DAC Volume similar to DACLVOL Read-only bit to indicate auto-muting 1: DAC auto-muted 0: DAC not muted DAC Auto-Mute Enable 1: Automatically mutes analogue output of stereo DAC if digital input is zero 0: Auto-mute OFF
4:0 5Ch Additional Functions (1) 15
DACR VOL AMUTE
01000 (0dB) 0
7
AMEN
0
Table 11 Stereo DAC Volume Control
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TONE CONTROL / BASS BOOST
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The WM9715L provides separate controls for bass and treble with programmable gains and filter characteristics. This function operates on digital audio data before it is passed to the audio DACs. Bass control can take two different forms: * Linear bass control: bass signals are amplified or attenuated by a user programmable gain. This is independent of signal volume, and very high bass gains on loud signals may lead to signal clipping. Adaptive bass boost: The bass volume is amplified by a variable gain. When the bass volume is low, it is boosted more than when the bass volume is high. This method is recommended because it prevents clipping, and usually sounds more pleasant to the human ear.
*
Treble control applies a user programmable gain, without any adaptive boost function. Treble, linear bass and 3D enhancement can all produce signals that exceed full-scale. In order to avoid limiting under these conditions, it is recommended to set the DAT bit to attenuate the digital input signal by 6dB. The gain at the outputs should be increased by 6dB to compensate for the attenuation. Cut-only tone adjustment and adaptive bass boost cannot produce signals above fullscale and therefore do not require the DAT bit to be set. REGISTER ADDRESS 08h DAC Tone Control BIT 15 LABEL BB DEFAULT 0 DESCRIPTION Bass Mode 0 = Linear bass control 1 = Adaptive bass boost Bass Cut-off Frequency 0 = Low (130Hz at 48kHz sampling) 1 = High (200Hz at 48kHz sampling) Bass Intensity Code 0000 0001 0010 ... 0111 ... 1011-1101 1110 1111 6 DAT 0 BB=0 +9dB +9dB +7.5dB (1.5dB steps) 0dB (1.5dB steps) -6dB -6dB Bypass (OFF) BB=1 15 (max) 14 13 ... 8 ... 4-2 1 (min)
12
BC
0
11:8
BASS
1111 (OFF)
-6dB attenuation 0 = Off 1 = On Treble Cut-off Frequency 0 = High (8kHz at 48kHz sampling) 1 = Low (4kHz at 48kHz sampling) Treble Intensity 0000 or 0001 = +9dB 0010 = +7.5dB ... (1.5dB steps) 1011 to 1110 = -6dB 1111 = Treble Control Disabled
4
TC
0
3:0
TRBL
1111 (Disabled)
Table 12 DAC Tone Control Note: 1. All cut-off frequencies change proportionally with the DAC sample rate.
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3D STEREO ENHANCEMENT
The 3D stereo enhancement function artificially increases the separation between the left and right channels by amplifying the (L-R) difference signal in the frequency range where the human ear is sensitive to directionality. The programmable 3D depth setting controls the degree of stereo expansion introduced by the function. Additionally, the upper and lower limits of the frequency range used for 3D enhancement can be selected using the 3DFILT control bits. REGISTER ADDRESS 20h General Purpose 22h DAC 3D Control BIT 13 LABEL 3DE DEFAULT 0 (disabled) 0 DESCRIPTION 3D enhancement enable
5
3DLC
Lower Cut-off Frequency 0 = Low (200Hz at 48kHz sampling) 1 = High (500Hz at 48kHz sampling) Upper Cut-off Frequency 0 = High (2.2kHz at 48kHz sampling) 1 = Low (1.5kHz at 48kHz sampling) 3D Depth 0000: 0% (minimum 3D effect) 0001: 6.67% ... 1110: 93.3% 1111: 100% (maximum)
4
3DUC
0
3:0
3DDEPTH
0000
Table 13 Stereo Enhancement Control Note: 1. All cut-off frequencies change proportionally with the DAC sample rate.
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AUXILIARY DAC
Production Data
AUXDAC is a simple 12-bit mono DAC. It can be used to generate DC signals (with the numeric input written into a control register), or AC signals such as telephone-quality ring tones or system beeps (with the input signal supplied through an AC-Link slot). In AC mode (XSLE = 1), the input data is binary offset coded; in DC mode (XSLE = 0), there is no offset. The analogue output of AUXDAC is routed directly into the output mixers. The signal gain into each mixer can be adjusted at the mixer inputs using control register 12h. In slot mode (XSLE = 1), the AUXDAC also supports variable sample rates (See "Variable Rate Audio" section). When the auxiliary DAC is not used, it can be powered down by setting AXE = 0. This is also the default setting. REGISTER ADDRESS 64h AUDAC Input Control BIT 15 LABEL XSLE DEFAULT 0 DESCRIPTION AUXDAC input selection 0: from AUXDACVAL (for DC signals) 1: from AC-Link slot selected by AUXDACSLT (for AC signals) AUXDAC Input Selection 000 - Slot 5, bits 8-19 (with XSLE=1) 001 - Slot 6, bits 8-19 (with XSLE=1) 010 - Slot 7, bits 8-19 (with XSLE=1) 011 - Slot 8, bits 8-19 (with XSLE=1) 100 - Slot 9, bits 8-19 (with XSLE=1) 101 - Slot 10, bits 8-19 (with XSLE=1) 110 - Slot 11, bits 8-19 (with XSLE=1) 111 - RESERVED (do not use) AUXDAC Digital Input (with XSLE=0) 000h: minimum FFFh: full-scale Mute AUXDAC path to headphone mixer 1: Mute, 0: No mute (ON) AUXDAC to headphone mixer gain 000: +6dB ... (3dB steps) 111: -15dB Mute AUXDAC path to speaker mixer 1: Mute, 0: No mute (ON) AUXDAC to speaker mixer gain 000: +6dB ... (3dB steps) 111: -15dB Mute AUXDAC path to phone mixer 1: Mute, 0: No mute (ON) AUXDAC to phone mixer gain 000: +6dB ... (3dB steps) 111: -15dB 0: AUXDAC off 1: AUXDAC enabled
14:12
AUXDAC SLT
000
11:0
AUXDAC VAL A2H
000h
12h AUXDAC Output Control
15
1
14:12
A2HVOL
010 (0dB)
11 10:8
A2S A2SVOL
1 010 (0dB)
7 6:4
A2P A2PVOL
1 010 (0dB)
0 Table 14 AUXDAC Control
AXE
0
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Note that at low DCVDD voltages, the output range of the AUXDAC becomes limited, so that its maximum RMS output voltage is the lesser of: (DCVDD-0.7) / 2 Vrms or AVDD / 3.3 Vrms Under these circumstances, the AUXDAC cannot convert high digital input values to the correct analogue equivalent; its digital input range must therefore be limited accordingly. If necessary, this limitation can be circumvented by setting gains for the AUXDAC signal in register 12h, or by using a higher DCVDD voltage.
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WM9715L ANALOGUE AUDIO OUTPUTS
Production Data
The following sections give an overview of the analogue audio output pins. For more information on recommended external components, please refer to the "Applications Information" section.
HEADPHONE OUTPUTS - HPOUTL AND HPOUTR
The HPOUTL and HPOUTR (pins 39 and 41) are designed to drive a 16 or 32 headphone or a line output. They can also be used as line-out pins. The output signal is produced by the headphone mixer. The signal volume on HPOUTL and HPOUTR can be independently adjusted under software control by writing to register 04h. When HPOUTL and HPOUTR are not used, the output drivers can be disabled to save power (see "Power Management" section). Both pins remain at the same DC level (the reference voltage VREF) when they are disabled, so that no click noise is produced. REGISTER ADDRESS 04h HPOUTL / HPOUTR Volume BIT 15 LABEL MUTE DEFAULT 1 DESCRIPTION Mute HPOUTL and HPOUTR 1: Mute (OFF) 0: No Mute (ON) HPOUTL Volume 000000: 0dB (maximum) 000001: -1.5dB ... (1.5dB steps) 011111: -46.5dB 1xxxxx: -46.5dB Zero Cross Enable 0: Change gain immediately 1: Change gain only on zero crossings, or after time-out HPOUTR Volume Similar to HPOUTLVOL
13:8
HPOUTLVOL
000000 (0dB)
7
ZC
0
5:0
HPOUTRVOL
00000 (0dB)
Table 15 HPOUTL / HPOUTR Control
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Pin 37 (OUT3) has a buffer that can drive load impedances down to 16. It can be used to: * Drive an ear speaker (phone receiver). The speaker can be connected differentially between OUT3 and HPOUTL, or in single-ended configuration (OUT3 to HPGND). The ear speaker output is produced by the headphone mixer. The right signal must be inverted (OUT3INV = 1), so that the left and right channel are mixed to mono in the speaker [L-(-R) = L+R]. Eliminate the DC blocking capacitors on HPOUTL and HPOUTR. In this configuration, OUT3 produces a buffered midrail voltage (AVDD/2) and is connected to the headphone socket's ground pin (see "Applications Information") Produce the inverse of the MONOOUT signal, for a differential mono output.
EAR SPEAKER OUTPUT - OUT3
*
*
Note: OUT3 can only handle one of the above functions at any given time. REGISTER ADDRESS 16h OUT3 Control BIT 15 LABEL MUTE DEFAULT 1 DESCRIPTION Mute OUT3 1: Mute (Buffer OFF) 0: No Mute (Buffer ON) Source of OUT3 signal 00 01 10 11 7 ZC 0 inverse of HPOUTR (for BTL ear speaker) VREF (for capless headphone drive) mono mix of both headphone channels (for single-ended ear speaker) inverse of MONOOUT (for differential mono output)
10:9
OUT3 SRC
00
Zero Cross Enable 0: Change gain immediately 1: Change gain only on zero crossings, or after time-out OUT3 Volume 000000: 0dB (maximum) 000001: -1.5dB ... (1.5dB steps) 011111: -46.5dB 1xxxxx: -46.5dB
5:0
OUT3 VOL
000000 (0dB)
Table 16 OUT3 Control
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LOUDSPEAKER OUTPUTS - LOUT2 AND ROUT2
Production Data
The LOUT2 and ROUT2 outputs are designed to differentially drive an 8 mono speaker. They can also be used as a stereo line-out or headphone output. For speaker drive, the LOUT2 signal must be inverted (INV = 1), so that the left and right channel are added up in the speaker [R-(-L) = R+L]. REGISTER ADDRESS 02h LOUT2/ROUT2 Volume BIT 15 LABEL MUTE DEFAULT 1 DESCRIPTION Mute LOUT2 and ROUT2 1: Mute (OFF) 0: No Mute (ON) LOUT2 Volume 000000: 0dB (maximum) 000001: -1.5dB ... (1.5dB steps) 011111: -46.5dB 1xxxxx: -46.5dB Zero Cross Enable 0: Change gain immediately 1: Change gain only on zero crossings, or after time-out LOUT2 Invert 0 = No Inversion (0 phase shift) 1 = Signal inverted (180 phase shift) ROUT2 Volume Similar to LOUT2VOL Source of LOUT2/ROUT2 signals 0: speaker mixer (for BTL speaker) 1: headphone mixer (for stereo output)
13:8
LOUT2VOL
00000 (0dB)
7
ZC
0
6
INV
0
5:0 16h 8
ROUT2VOL SRC
00000 (0dB) 0
Table 17 LOUT2 / ROUT2 Control Note: 1. For BTL speaker drive, it is recommended that LOUT2VOL = ROUT2VOL.
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The MONOOUT output (pin 33) is intended for connection to the TX side of a wireless chipset. The signal is generated in a dedicated mono mixer; it is not necessarily a mono mix of the stereo outputs HPOUTL/R or LOUT2/ROUT2 (see "Audio Mixers" section). The MONOOUT volume can be controlled by writing to register 06h. When MONOOUT is not used, the output buffer can be disabled to save power (see "Power Management" section). The MONOOUT pin remains at the same DC level (the reference voltage on the VREF pin), so that no click noise is produced when muting or un-muting. REGISTER ADDRESS 06h MONOOUT Volume BIT 15 LABEL MUTE DEFAULT 1 DESCRIPTION Mute MONOOUT 1: Mute 0: No Mute Zero Cross Enable 0: Change gain immediately 1: Change gain only on zero crossings, or after time-out MONOOUT Volume 00000: 0dB (maximum) 00001: -1.5dB ... (1.5dB steps) 11111: -46.5dB
PHONE OUTPUT (MONOOUT)
7
ZC
0
4:0
MONOOUT VOL
00000 (0dB)
Table 18 MONOOUT Control
THERMAL SENSOR
The speaker and headphone outputs can drive very large currents. To protect the WM9715L from becoming too hot, a thermal sensor has been built in. If the chip temperature reaches approximately 150C, and the ENT bit is set, the WM9715L de-asserts bit 11 in register 54h, which can be set up to generate an interrupt to the CPU (see "Interrupt Control" section). REGISTER ADDRESS 5Ch BIT 2 LABEL ENT DEFAULT 0 DESCRIPTION Enable thermal sensor 0: Disabled 1: Enabled Thermal sensor (interrupt bit) 1: Temperature below 150C 0: Temperature above 150C See also "Interrupt Control" section.
54h
11
TI
1
Table 19 Thermal Cutout Control
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DIGITAL AUDIO (SPDIF) OUTPUT
The WM9715L supports the SPDIF standard using the SPDIF_OUT pin as its output.
Production Data
Register 3Ah is a read/write register that controls SPDIF functionality and manages bit fields propagated as channel status (or sub-frame in the V case). With the exception of V, this register should only be written to when the SPDIF transmitter is disabled (SPDIF bit in register 2Ah is `0'). Once the desired values have been written to this register, the contents should be read back to ensure that the sample rate in particular is supported, then SPDIF validity bit SPCV in register 2Ah should be read to ensure the desired configuration is valid. Only then should the SPDIF enable bit in register 2Ah be set. This ensures that control and status information start up correctly at the beginning of SPDIF transmission. REGISTER ADDRESS 2Ah Extended Audio BIT 10 5:4 LABEL SPCV SPSA DEFAULT 0 01 DESCRIPTION SPDIF validity bit (read-only) SPDIF slot assignment (ADCO = 0) 00: Slots 3, 4 01: Slots 6, 9 10: Slots 7, 8 11: Slots 10, 11 SPDIF output enable 1 = enabled, 0 = disabled Note: Bit 5 of register 4Ch and bit 5 of register 56h must be `0' before the SPDIF output can be enabled. Validity bit; `0' indicates frame valid, `1' indicates frame not valid Indicates that the WM9715L does not support double rate SPDIF output (read-only) Indicates that the WM9715L only supports 48kHz sampling on the SPDIF output (readonly) Generation level; programmed as required by user Category code; programmed as required by user Pre-emphasis; `0' indicates no pre-emphasis, `1' indicates 50/15us pre-emphasis Copyright; `0' indicates copyright is not asserted, `1' indicates copyright Non-audio; `0' indicates data is PCM, `1' indicates non-PCM format (e.g. DD or DTS) Professional; `0' indicates consumer, `1' indicates professional Source of SPDIF data 0: SPDIF data comes from SDATAOUT (pin 5), slot selected by SPSA 1: SPDIF data comes from audio ADC
2
SEN
0
3Ah SPDIF Control Register
15 14 13:12
V DRS SPSR
0 0 10
11 10:4 3 2 1 0 5Ch Additional Function Control 4
L CC PRE COPY AUDIB PRO ADCO
0 0000000 0 0 0 0 0
Table 20 SPDIF Output Control
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MIXER OVERVIEW
The WM9715L has three separate low-power audio mixers to cover all audio functions required by smartphones, PDAs and handheld computers. The diagram below shows the routing of the analogue audio signals into the mixers. The numbers at the mixer inputs refer to the control register bits that control the volume and muting for that particular signal.
0Eh [7]
AUDIO MIXERS
MICL MICR LINE_IN PCBEEP PHONE_IN
DIFF / STEREO/ MONO (Reg 20h)
0Eh [12:8,4:0]
0/20 dB
10h [12:8,4:0]
0Eh [14,13] 18h [13] 1Ah [13:11] 10h [13] 12h [7:4] 0Ah [7:4]
OUT3VOL (Reg 16h)
PHONE MIX
OUT3SRC (Reg 16h) VREF MONOOUT
MONOOUT (PHONE TX)
0Ch [4:0] 0Ch [15] 10h [15] 14h [11:7] 18h [15] 14h [15:12] 0Ah [15:12] 12h [15:12]
M U X
OUT3 ear speaker HPOUTL HPOUTR
HPVOL (Reg 04h)
STEREO
18h [12:8,4:0]
DAC
HEAD PHONE/ EAR SPEAKER MIX
INV (Reg 02h)
PHONE MIX
HEADPHONE MIX
M RECORD U X SELECT
1Ch / ALC
Stereo headphone / headset LOUT2 loud speaker
BACK SPKR MIX AUX DAC
(12-BIT)
0/20 dB
10h [14] 18h [14] 12h [11:8] 0Ah [11:8] 0Ch [14]
STEREO
-1
BACK SPEAKER MIX
M U X
SRC (Reg 16h) OUT2VOL (Reg 02h)
ROUT2
1Ah [14]
ADC
Figure 4 Audio Mixer Overview
HEADPHONE MIXER
The headphone mixer drives the HPOUTL and HPOUTR outputs. It also drives OUT3, if this pin is connected to an ear speaker (phone receiver). The following signals can be mixed into the headphone path: * * * * * * * PHONE (controlled by register 0Ch, see "Audio Inputs") LINE_IN (controlled by register 10h, see "Audio Inputs") the output of the Record PGA (see "Audio ADC", "Record Gain") the stereo DAC signal (controlled by register 18h, see "Audio DACs") the MIC signal (controlled by register 0Eh, see "Audio Inputs") PC_BEEP (controlled by register 0Ah, see "Audio Inputs") the AUXDAC signal (controlled by register 12h, see "Auxiliary DAC")
In a typical smartphone application, the headphone signal is a mix of PHONE and sidetone (for phone calls) and the stereo DAC signal (for music playback).
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SPEAKER MIXER
Production Data
The speaker mixer drives the LOUT2 and ROUT2 output. The following signals can be mixed into the speaker path: * * * * * PHONE (controlled by register 0Ch, see "Audio Inputs") LINE_IN (controlled by register 10h, see "Audio Inputs") the stereo DAC signal (controlled by register 18h, see "Audio DACs") PC_BEEP (controlled by register 0Ah, see "Audio Inputs") the AUXDAC signal (controlled by register 12h, see "Auxiliary DAC")
In a typical smartphone application, the speaker signal is a mix of AUXDAC (for system alerts or ring tone playback), PHONE (for speakerphone function), and PC_BEEP (for externally generated ring tones).
MONO MIXER
The mono mixer drives the MONOOUT pin. The following signals can be mixed into MONOOUT: * * * * * * LINE_IN (controlled by register 10h, see "Audio Inputs") the output of the Record PGA (see "Audio ADC", "Record Gain") the stereo DAC signal (controlled by register 18h, see "Audio DACs") the MIC signal (controlled by register 10h, see "Audio Inputs") PC_BEEP (controlled by register 0Ah, see "Audio Inputs") the AUXDAC signal (controlled by register 12h, see "Auxiliary DAC")
In a typical smartphone application, the MONOOUT signal is a mix of the amplified microphone signal (possibly with Automatic Gain Control) and (if enabled) an audio playback signal from the stereo DAC or the auxiliary DAC.
SIDE TONE CONTROL
The side tone path is into the headphone mixer and is either from the MIC or ALC path (with no 20dB boost) REGISTER ADDRESS 14h Sidetone Control 15 BIT LABEL STM DEFAULT 1 DESCRIPTION MIC side tone select 0: selected 1 : not selected (path muted) MIC Sidetone volume 000 : +6dB (max.) 001: +3dB ... (3dB steps) 111 : -15dB (min.) ALC side tone select 11: mute 10: mono - left 01: mono - right 00: stereo ALC Sidetone volume Similar to STVOL
14:12
STVOL
010 (0dB)
11:10
ALCM
11
9:7 Table 21 Side Tone Control
ALCVOL
010 (0dB)
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VARIABLE RATE AUDIO / SAMPLE RATE CONVERSION
By using an AC'97 Rev2.2 compliant audio interface, the WM9715L can record and playback at all commonly used audio sample rates, and offer full split-rate support (i.e. the DAC, ADC and AUXDAC sample rates are completely independent of each other - any combination is possible). The default sample rate is 48kHz. If the VRA bit in register 2Ah is set and the appropriate block is enabled, then other sample rates can be selected by writing to registers 2Ch, 32h and 2Eh. The ACLink continues to run at 48k frames per second irrespective of the sample rate selected. However, if the sample rate is less than 48kHz, then some frames do not carry an audio sample. REGISTER ADDRESS 2Ah Extended Audio Stat/Ctrl 2Ch Audio DAC Sample Rate 0 BIT LABEL VRA DEFAULT 0 (OFF) DESCRIPTION Variable Rate Audio 0: OFF (DAC and ADC run at 48kHz) 1: ON (sample rates determined by registers 2Ch, 2Eh and 32h) Audio DAC sample rate 1F40h: 8kHz 2B11h: 11.025kHz 2EE0h: 12kHz 3E80h: 16kHz 5622h: 22.05kHz 5DC0h: 24kHz 7D00h: 32kHz AC44h: 44.1kHz BB80h: 48kHz Any other value defaults to the nearest supported sample rate Audio ADC sample rate similar to DACSR Note writing to these bits has no effect when ADC is disabled AUXDAC sample rate similar to DACSR
15:0
DACSR
BB80h (48kHz)
32h Audio ADC Sample Rate 2Eh AUXDAC Sample Rate
15:0
ADCSR
BB80h (48kHz)
15:0
AUXDAC SR
BB80h (48kHz)
Table 22 Audio Sample Rate Control When the audio ADC is disabled, its sample rate cannot be changed (i.e. writing to the ADCSR bits has no effect). The following sequence of register writes is therefore recommended for changing the ADC sample rate: 1. Set PD11 and/or PD12 = 0 in register 24h as appropriate for left/right/stereo ADC operation Set PR0 = 0 in register 26h to enable the audio ADC(s) Set VRA = 1 in register 2Ah to enable Variable Rate Audio Set ADCSR in register 32h to the appropriate value for the desired sample rate
2. 3. 4.
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WM9715L TOUCHPANEL INTERFACE
Production Data
The WM9715L includes a touchpanel driver and digitiser circuit for use with 4-wire or 5-wire resistive touchpanels. The following functions are implemented: * * * * * X co-ordinate measurement Y co-ordinate measurement Pen down detection, with programmable sensitivity Touch pressure measurement (4-wire touchpanel only) Auxiliary measurement from COMP1/AUX1 (pin 29), COMP2/AUX2 (pin 30), BMON/AUX3 (pin 31), or WIPER/AUX4 (pin 12)
The touchpanel digitiser uses a very low power, 12-bit successive approximation type ADC. The same ADC can also be used for battery and auxiliary measurements (see the "Battery Alarm and Battery Measurement" and "Auxiliary ADC Inputs" sections). An on-chip switch matrix connects each touchpanel terminal to the supply voltage TPVDD, to ground (TPGND), or to the ADC input, as required.
RPU IP zero power comparator PEN DOWN
SAR ADC
20K
10K
TPVDD
TPGND
Figure 5 Touchpanel Switch Matrix
PRINCIPLE OF OPERATION - FOUR-WIRE TOUCHPANEL
Four-wire touchpanels are connected to the WM9715L as follows: * * * * Right side contact = X+ (pin 14) Left side contact = X- (pin 16) Top side contact = Y+ (pin 15) Bottom side contact = Y- (pin 17)
X+/BR (14) X-/TL (16) Y+/TR (15) Y-/BL (17) WIPER/AUX4 (12) AUX1 (29) AUX2 (30) AUX3/BMON (31)
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The principle of operation is illustrated below (Note: the illustrations assume that the top plate is used for X and the bottom plate for Y measurements, although the reverse is also possible).
Figure 6 X Co-ordinate Measurement on 4-wire Touchpanel For an X co-ordinate measurement, the X+ pin is internally switched to VDD and X- to GND. The X plate becomes a potential divider, and the voltage at the point of contact is proportional to its X coordinate. This voltage is measured on the Y+ and Y- pins, which carry no current (hence there is no voltage drop in RY+ or RY-). Due to the ratiometric measurement method, the supply voltage does not affect measurement accuracy. The voltage references VREF+ and VREF- are taken from after the matrix switches, so that any voltage drop in these switches has no effect on the ADC measurement.
Figure 7 Y Co-ordinate Measurement on 4-wire Touchpanel Y co-ordinate measurements are similar to X co-ordinate measurements, with the X and Y plates interchanged.
Figure 8 Pen Down Detection on 4-wire Touchpanel Pen down detection uses a zero power comparator (effectively a CMOS logic gate) with an internal, programmable pull-up resistor RPU that controls pen-down sensitivity. Increasing RPU makes the touchpanel less sensitive to touch, while lowering RPU makes it more sensitive.
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the comparator output goes high.
Production Data When the touchpanel is not being touched, no current flows in the circuit, and the PENDOWN signal is low. When the panel is touched with a pen or finger, current flows through RPU and the panel, and
The PENDOWN signal can be transmitted through the PENDOWN pin (see "Interrupt Control" section). Additionally, its state is reflected in the PNDN bit (register 7Ah, bit 15) and the interrupt logic block (register 54h, bit 13), where it can wake the WM9715L from sleep mode (see "Interrupt Control" section).
Figure 9 Touch Pressure Measurement on 4-wire Touchpanel Touch pressure can be determined indirectly by measuring the contact resistance RC between the top and bottom plates. RC decreases as the touch pressure on the panel increases. The WM9715L measures RC by sending a constant current IP through the touchpanel and measuring the potential on each plate. The two values are subtracted in the digital domain to obtain the potential difference, which is proportional to RC. To suit different types of touchpanels, the magnitude of IP can be set to either 400A or 200A using the PIL control bit.
PRINCIPLE OF OPERATION - FIVE-WIRE TOUCHPANEL
Five-wire touchpanels are connected to the WM9715Las follows: * * * * * Top sheet contact = WIPER/AUX4 (pin 12) Top left corner of bottom sheet = TL (pin 16) Top right corner of bottom sheet = TR (pin 15) Bottom left corner of bottom sheet = BL (pin 17) Bottom right corner of bottom sheet = BR (pin 14)
Figure 10 X Co-ordinate Measurement on 5-wire Touchpanel
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For an X co-ordinate measurement, the top left and bottom left corners of the touchpanel are grounded internally to the WM9715, while the top right and bottom right contacts are connected to TPVDD. The bottom plate becomes a potential divider with a voltage gradient in the X direction. The voltage at the point of contact is proportional to its X co-ordinate. This voltage is measured on the TOP pin and converted to a digital value by the ADC. Due to the ratiometric measurement method, the supply voltage does not affect measurement accuracy. The voltage references VREF+ and VREF- are taken from after the matrix switches, so that any voltage drop in these switches has no effect on the ADC measurement.
Figure 11 Y Co-ordinate Measurement on 5-wire Touchpanel Y co-ordinate measurements are similar to Y co-ordinate measurements. However, the voltage gradient on the bottom plate is in the Y direction instead of the X direction. This is achieved by grounding the bottom left and bottom right corners of the touchpanel, and connecting the top left and top right contacts to TPVDD.
Figure 12 Pen Down Detection on 5-wire Touchpanel Pen down detection works in a similar fashion for both 4-wire and 5-wire touchpanels (see Four-Wire Touchpanel Operation). On a 5-wire touchpanel, all four contacts of the bottom plate are grounded, and the top plate contact is connected to the internal programmable pull-up resistor, RPU.
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CONTROLLING THE TOUCHPANEL DIGITISER
All touchpanel functions are accessed and controlled through the AC-Link interface. PHYSICAL CHARACTERISTICS
Production Data
The physical characteristics of the touchpanel interface are controlled through register 78, as shown below. REGISTER ADDRESS 78h BIT 12 LABEL 45W DEFAULT 0 (4-wire) DESCRIPTION Touchpanel Type Selection 0: 4-wire 1: 5-wire Internal Pull-up resistor for Pen Detection 000000: RESERVED (do not use this setting) 000001: RPU/1 = TYP 68k (most sensitive) 000010: RPU /2 = TYP 34k ... (pull-up = RPU / binary value of RPU) (Refer to page 9 for RPU specification) Current used for pressure measurement 0: IP = 200A 1: IP = 400A
0:5
RPU
000001 (68k)
8
PIL
0 (200A)
Table 23 Touchpanel Digitiser Control (Physical Characteristics)
POWER MANAGEMENT
To save power, the touchpanel digitiser and the pen-down detector can be independently disabled when they are not used. The power consumption of the pen-down detector is normally negligible, except when the pen is down. The state of the digitiser and pen down detector is controlled by the following bits. REGISTER ADDRESS 78h BIT 15:14 LABEL PRP DEFAULT 00 DESCRIPTION Pen ADC/AUX ADC enable 00 - Pen digitiser off, pen detect off, no wake-up on pen down (default) 01 - Pen digitiser powered off, pen detect enabled, touchpanel digitiser wakes up (changes to state 11) on pen-down 10 - Pen digitiser off, pen detect enabled, no wake-up on pen down 11 - Pen digitiser and pen detect enabled Wake-up on pen-down mode 0: Wake-up the AC-Link only (hold SDATAIN high until controller sends warm reset or cold reset) 1: Wake-up the WM9715L without waiting for a reset signal from the controller
13
RPR
0
Table 24 Touchpanel Digitiser Control (Power Management)
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INITIATION OF MEASUREMENTS
The WM9715L touchpanel interface supports both polling routines and DMA (direct memory access) to control the flow of data from the touchpanel ADC to the host CPU. In a polling routine, the CPU starts each measurement individually by writing to the POLL bit (register 76h, bit 15). This bit automatically resets itself when the measurement is completed. REGISTER ADDRESS 76h 10 15 9:8 BIT LABEL CTC POLL CR DEFAULT 0 0 00 DESCRIPTION 0: Polling mode 1: Continuous mode (for DMA) Writing "1" initiates a measurement Continuous mode rate (DEL 1111) 00: 93.75 Hz (every 512 AC-Link frames) 01: 187.5 Hz (every 256 AC-Link frames) 10: 375Hz (every 128 AC-Link frames) 11: 750Hz (every 64 AC-Link frames) Continuous mode rate (DEL = 1111) 00: 8 kHz (every six AC-Link frames) 01: 12 kHz (every four AC-Link frames) 10: 24 kHz (every other AC-Link frame) 11: 48 kHz (every AC-Link frame) 0: measure regardless of pen status 1: measure only when pen is down (when CTC=0 and POLL=1, measurement is delayed until pen-down; when CTC=1, measurements are stopped on pen-up)
78h
11
PDEN
0
Table 25 Touchpanel Digitiser Control (Initiation of Measurements) In continuous mode (CTC = 1), the WM9715L autonomously initiates measurements at the rate set by CR, and supplies the measured data to the CPU on one of the unused AC'97 time slots. DMAenabled CPUs can write the data directly into a FIFO without any intervention by the CPU core. This reduces CPU loading and speeds up the execution of user programs in handheld systems. Note that the measurement frequency in continuous mode is also affected by the DEL bits (see "Touchpanel Settling Time"). The faster rates achieved when DEL = 1111 may be useful when the ADC is used for auxiliary measurements.
MEASUREMENT TYPES
The ADCSEL control bits determine which type of measurement is performed (see below). REGISTER ADDRESS 76h BIT 14:12 LABEL ADCSEL DEFAULT 000 DESCRIPTION Measurement Type (ADC Input Selector) 000: No measurement 001: X co-ordinate measurement 010: Y co-ordinate measurement 011: Pressure measurement 100: COMP1/AUX1 measurement (pin 29) 101: COMP2/AUX2 measurement (pin 30) 110: BMON/AUX3 measurement (pin 31) 111: WIPER/AUX4 measurement (pin 12) Enable co-ordinate mode 0: Single measurement according to ADCSEL 1: X, then Y, then additional measurement indicated by ADCSEL
11
COO
0
Table 26 Touchpanel Digitiser Control (Measurement Types)
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Production Data When COO is `0', the WM9715L performs one type of measurement once (in polling mode) or continuously (in continuous mode). The co-ordinate mode (COO = `1') makes it easier to obtain co-ordinate pairs rather than single coordinates. In polling-coordinate mode (CTC = `0', COO = `1'), the WM9715L performs an X measurement, followed by a Y measurement, followed by an additional measurement determined by ADCSEL, then stops. In continuous-coordinate mode (CTC = `1', COO = `1'), the WM9715L continuously repeats a sequence consisting of an X-co-ordinate measurement, followed by a Y coordinate measurement, followed by an additional measurement determined by ADCSEL (if ADCSEL = 000, the sequence is XYXYXY... only).
DATA READBACK
The output data word of the touchpanel interface consists of three parts: * Pen Status (1 bit) - this is also passed to the interrupt logic block, which can be programmed to generate an interrupt and/or wake up the WM9715L on pen down (see "Interrupt Control"). Output data from the touchpanel ADC (12 bits) ADCSRC: 3 additional bits that indicate the source of the ADC data. With COO = `0', ADCSRC echoes ADCSEL. However, in co-ordinate mode (COO = `1'), the WM9715L schedules different types of measurements autonomously and sets the ADCSRC bits accordingly (see "Measurement Types").
* *
This data is stored in register 7Ah, and can be retrieved by reading the register in the usual manner (see AC-Link Interface section). Additionally, the data can also be passed to the controller on one of the AC-Link time slots not used for audio functions. To minimize CPU loading, it is recommended to use interrupt-driven methods rather than polling routines for reading touchpanel data. However, where polling routines are used, two methods are available for determining when a measurement has finished: * * Reading back the POLL bit. If it has been reset to `0', then the measurement has finished. Reading back 7Ah until the new data appears REGISTER ADDRESS 7Ah or AC-Link slot selected by SLT BIT 15 LABEL PNDN DEFAULT 0 DESCRIPTION Pen status (read-only) 0: Pen Up 1: Pen Down Touchpanel ADC Source 000: No measurement 001: X co-ordinate measurement 010: Y co-ordinate measurement 011: Pressure measurement (4-wire touchpanels only) 100: COMP1/AUX1 measurement (pin 29) 101: COMP2/AUX2 measurement (pin 30) 110: BMON/AUX3 measurement (pin 31) 111: WIPER/AUX4 measurement (pin 12) Touchpanel ADC Data (read-only) Bit 11 = MSB Bit 0 = LSB 0: No effect (new ADC data overwrites unread data in register 7Ah) 1: New data is held back, and measurements delayed, until register 7Ah is read)
14:12
ADCSRC
000
11:0
ADCD
000h
78h
9
WAIT
0
Table 27 Touchpanel Digitiser Data To avoid losing data that has not yet been read, the WM9715L can delay overwriting register 7Ah with new data until the old data has been read. This function is enabled using the WAIT bit.
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WM9715L
If the SLEN bit is set to `1', then the touchpanel data appears on the AC-Link slot selected by the SLT control bits, as shown below. The Slot 0 `tag' bit corresponding to the selected time slot is asserted whenever there is new data on that slot. REGISTER ADDRESS 76h BIT 3 LABEL SLEN DEFAULT 0 DESCRIPTION Slot Readback Enable 0: Disabled (readback through register only) 1: Enable (readback slot selected by SLT) AC'97 Slot Selection for Touchpanel Data 000: Slot 5 001: Slot 6 ... 101: Slot 10 110: Slot 11 111: RESERVED
2:0
SLT
110
Table 28 Returning Touchpanel Data Through an AC-Link Time Slot
TOUCHPANEL SETTLING TIME
For accurate touchpanel measurements, some settling time may be required between the switch matrix applying a voltage across the touchpanel plate and the ADC sampling the signal. This time delay function is built into the WM9715L and can be programmed as shown below. REGISTER ADDRESS 76h BIT 7:4 LABEL DEL DEFAULT 0000 (1 frame) DESCRIPTION Touchpanel ADC Settling Time
Table 29 Touchpanel Settling Time Control (1)
DEL 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
DELAY (AC-LINK FRAMES) 1 2 4 8 16 32 48 64 96 128 160 192 224 256 288
DELAY (TIME) 20.8s 41.7s 83.3s 167s 333s 667s 1ms 1.33ms 2ms 2.67ms 3.33ms 4ms 4.67ms 5.33ms 6ms
No delay, switch matrix always on
Table 30 Touchpanel Settling Time Control (2) The total time for co-ordinate or auxiliary measurements to complete is the delay time DEL, plus one AC-Link frame (20.8s). For a pressure measurement, the time taken is DEL plus two AC-Link frames (41.6s).
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Production Data Setting DEL to `1111' reduces the settling time to zero, i.e. measurements begin immediately. This mode is intended for fast sampling on AUX inputs. It is NOT intended for touchpanel digitisation. There are several side-effects when DEL is set to `1111': * * Co-ordinate mode does not work, i.e. the WM9715L behaves as if COO = 0, even if COO = 1 (see "Measurement Types") If X / Y co-ordinate or touch pressure measurements are selected (ADCSEL = 001, 010 or 011), then the switch matrix is constantly on, and current constantly flows in the touchpanel. This increases power consumption in the system, and is therefore not recommended for battery powered systems In continuous mode (CTC = 1), setting DEL = 1111 increases the sampling rate of the touchpanel ADC (see "Initiation of Measurements")
*
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WM9715L
AUXILIARY ADC INPUTS
The ADC used for touchpanel digitisation can also be used for auxiliary measurements, provided that it is enabled (register 78h, PRP = 11). The WM9715L has four pins that can be used as auxiliary ADC inputs: * * * * COMP1 / AUX1 (pin 29) COMP2 / AUX2 (pin 30) BMON / AUX3 (pin 31) WIPER / AUX4 (pin 12)
Note that pin 12 connects to the wiper of a 5-wire touchpanel wiper function. Auxiliary measurements taken on pin 12 are only meaningful when it is not connected to a touchpanel (i.e. a 4-wire touchpanel, or no touchpanel at all, is used). Pins 29 and 30 are also used as comparator inputs (see Battery Alarm and Battery Measurement), but auxiliary measurements can still be taken on these pins at any time. For the use of pin 31 see the "Battery Alarm And Battery Measurement" section, note that the measured value from the BMON/AUX3 pin will be 1/3 of the actual value due to the potential divider on this pin. The ADCSEL control bits select between different ADC inputs, as shown below. REGISTER ADDRESS 76h Touchpanel Digitiser Control BIT 14:12 LABEL ADCSEL DEFAULT 000 DESCRIPTION Touchpanel ADC Input Selector 000: No measurement 001-011: Touchpanel measurement (please refer to Touchpanel Digitiser section) 100: COMP1 / AUX1 measurement (pin 29) 101: COMP2 AUX2 measurement (pin 30) 110: BMON / AUX3 measurement (pin 31) 111: WIPER / AUX 4 measurement (pin 12)
Table 31 Auxiliary ADC Measurements Auxiliary ADC measurements are initiated in the same way as touchpanel measurements, and the data is returned in the same manner. Please refer to the "Controlling the Touchpanel Interface" section.
BATTERY MEASUREMENT USING THE BMON/AUX3 PIN
BMON/AUX3 (pin 31) has the capability to take inputs up to 5 volts (Assuming AVDD=3.3V) by dividing down the input signal. The internal potential divider has a total resistance of 30k. However, it is only connected to the pin when an AUX3 measurement is requested, and remains connected for the duration of one AC-Link frame (20.83s, assuming a 24.576MHz clock crystal is used). The effective input impedance of BMON/AUX3 is therefore given by: RBMON = 30k x 48kHz / [BMON sampling rate] For example, if BMON is sampled ten times per second, the effective input resistance is 30k x 48kHz / 10Hz = 144M.
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WM9715L BATTERY ALARM AND ANALOGUE COMPARATORS
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The battery alarm function differs from battery measurement in that it does not actually measure the battery voltage. Battery alarm only indicates "OK", "Low" or "Dead". The advantage of the battery alarm function is that it does not require a clock and can therefore be used in low-power sleep or standby modes.
Figure 13 Battery Alarm Example Schematic The typical schematic for a dual threshold battery alarm is shown above. This alarm has two thresholds, "dead battery" (COMP1) and "low battery" (COMP2). R1, R2 and R3 set the threshold voltages. Their values can be up to about 1M in order to keep the battery current [IALARM = VBATT / (R1+R2+R3)] to a minimum (higher resistor values may affect the accuracy of the system as leakage currents into the input pins become significant). * Dead battery alarm: COMP1 triggers when VBATT < VREF x (R1+R2+R3) / (R2+R3)
A dead battery alarm is the highest priority of interrupt in the system. It should immediately save all unsaved data and shut down the system. The GP15, GS15 and GW15 bits must be set to generate this interrupt. * Low battery alarm: COMP2 triggers when VBATT < VREF x (R1+R2+R3) / R3
A low battery alarm has a lower priority than a dead battery alarm. Since the threshold voltage is higher than for a dead battery alarm, there is enough power left in the battery to give the user a warning and/or shut down "gracefully". When VBATT gets close to the low battery threshold, spurious alarms are filtered out by the COMP2 delay function. The purpose of the capacitor C is to remove from the comparator inputs any high frequency noise or glitches that may be present on the battery (for example, noise generated by a charge pump). It forms a low pass filter with R1, R2 and R3. * Low pass cutoff fc [Hz] = 1/ (2 C x (R1 || (R2+R3)))
Provided that the cutoff frequency is several orders of magnitude lower than the noise frequency fn, this simple circuit can achieve excellent noise rejection. * Noise rejection [dB] = 20 log (fn / fc)
The circuit shown above also allows for measuring the battery voltage VBATT. This is achieved simply by setting the touchpanel ADC input to be either COMP1 (ADCSEL = 100) or COMP2 (ADCSEL = 101) (see also Auxiliary ADC Inputs).
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WM9715L
The WM9715L has two on-chip comparators that can be used to implement a battery alarm function, or other functions such as a window comparator. Each comparator has one of its inputs tied to any one of three device pins and the other tied to a voltage reference. The voltage reference can be either internally generated (VREF = AVDD/2) or externally connected on AUX4 (pin 12). The comparator output signals can be used to send an interrupt to the CPU via the GENIRQ pin, and / or to wake up the WM9715L from sleep mode (see "Interrupt Control" for details). REGISTER ADDRESS 4Eh BIT 15 LABEL CP1 DEFAULT 1 DESCRIPTION COMP1 Polarity (see also "Interrupt Control") 0: Alarm when COMP1 voltage is below VREF 1: Alarm when COMP1 voltage is above VREF COMP2 Polarity (see also "Interrupt Control") 0: Alarm when COMP2 voltage is below VREF 1: Alarm when COMP2 voltage is above VREF Low Battery Alarm Delay 000: No delay 001: 0.17s (213 = 8192 AC-Link frames) 14 010: 0.34s (2 = 16384 AC-Link frames) 011: 0.68s (215 = 32768 AC-Link frames) 100: 1.4s (216 = 65536 AC-Link frames) 17 101: 2.7s (2 = 131072 AC-Link frames) 110: 5.5s (218 = 262144 AC-Link frames) 111: 10.9s (219 = 524288 AC-Link frames)
14
CP2
1
58h
15:13
COMP2 DEL
0
Table 32 Comparator Control
REGISTER ADDRESS 5Ch Additional Analogue Functions
BIT 14
LABEL C1REF
DEFAULT 0
DESCRIPTION Comparator 1 Reference Voltage 0 1 VREF = AVDD/2 WIPER/AUX4 (pin 12) AVDD/2 when C1REF='1'. Otherwise comparator 1 is powered down COMP1/AUX1 (pin 29) COMP2/AUX2 (pin 30) BMON/AUX3 (pin 31) VREF = AVDD/2 WIPER/AUX4 (pin 12) AVDD/2 when C2REF='1'. Otherwise comparator 2 is powered down COMP1/AUX1 (pin 29) COMP2/AUX2 (pin 30) BMON/AUX3 (pin 31)
13:12
C1SRC
00
Comparator 1 Signal Source 00 01 10 11
11
C2REF
0
Comparator 2 Reference Voltage 0 1
10:9
C2SRC
00
Comparator 2 Signal Source 00 01 10 11
Table 33 Comparator Reference and Source Control
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COMP2 DELAY FUNCTION
Production Data
COMP2 has an optional delay function for use when the input signal is noisy. When COMP2 triggers and the delay is enabled (i.e. COMP2DEL is non-zero), then the C2I bit in register 54h does not change state immediately, and no interrupt is generated. Instead, the WM9715L starts a delay timer and checks COMP2 again after the delay time has passed. If COMP2 is still active, then the interrupt bit is set and an interrupt may be generated (depending on the state of the GW14 bit). If COMP2 is no longer active, the interrupt bit is not set, i.e. all register bits are as if COMP2 had never triggered. Note: If COMP2 triggers while the WM9715L is in sleep mode, and the delay is enabled, then the device starts the on-chip crystal oscillator in order to count the time delay.
COMP2 TRIGGERS
C2W?
0
END
1
COMP2 DEL?
non-zero
START TIMER
WAIT time=COMP2DEL 000 SHUT DOWN TIMER
COMP2?
Inactive
END [FALSE ALARM]
Active
SET GI14
END
Figure 14 COMP2 Delay Flow Chart
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INTERRUPT CONTROL
The WM9715L has three interrupt pins: * * * ADCIRQ is a dedicated interrupt pin to indicate that AUXADC data is available for reading (see "Touchpanel interface") PENDOWN is a dedicated interrupt pin to indicate that the resistive touchpanel connected to the WM9715L is being touched (see "Touchpanel interface") GENIRQ is a general-purpose interrupt pin, which can indicate a number of different events.
THE ADCIRQ PIN
In a typical use case with touchscreen measurements running continuously, "AUXADC data available" is the most frequent type of interrupt event from the WM9715L. In the interest of minimizing software overheads, it is recommended to use the dedicated ADCIRQ pin to transmit this type of interrupt. The ADCIRQ output is enabled using registers 56h and 4Ch. REGISTER ADDRESS 4Ch 56h BIT 4 4 LABEL GC4 GE4 DEFAULT 1 1 DESCRIPTION ADCIRQ output enable ADCIRQ is enabled when both GC4 and GE4 are set to `0'. To disable ADCIRQ, set both bits to `1'. Other combinations (0/1, 1/0) are reserved.
Table 34 Enabling the ADCIRQ pin
THE PENDOWN PIN
In a typical use case, PENDOWN is the second most frequent type of interrupt after ADCIRQ. In the interest of minimizing software overheads, it is recommended to use the dedicated PENDOWN pin to transmit this type of interrupt. The PENDOWN output is enabled using registers 56h and 4Ch. REGISTER ADDRESS 4Ch 56h BIT 3 3 LABEL GC3 GE3 DEFAULT 1 1 DESCRIPTION PENDOWN output enable PENDOWN is enabled when both GC4 and GE4 are set to `0'. To disable PENDOWN, set both bits to `1'. Other combinations (0/1, 1/0) are reserved.
Table 35 Enabling the PENDOWN pin
THE GENIRQ PIN
The GENIRQ pin transmits a logical OR of up to five individual interrupt events: * * * * * Over-temperature (see "Thermal Sensor") COMP1 events, e.g. dead battery alarm (see "Battery Alarm and Analogue Comparators") COMP2 events, e.g. low battery alarm (see "Battery Alarm and Analogue Comparators") ADCIRQ PENDOWN
When the host processor receives an interrupt, it needs to read register 54h in order to determine which event triggered the interrupt. As a result, GENIRQ is best suited for interrupts that occur rarely, and where longer response times can be tolerated. ADCIRQ or PENDOWN interrupts should only be
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Production Data transmitted through the GENIRQ pin if the dedicated interrupt pins cannot be used (e.g. if there are insufficient pins available on the host processor). The GENIRQ output is enabled using registers 56h and 4Ch. Its polarity can be controlled using the IRQINV bit in register 58h, and interrupt wake-up (i.e. re-activating the AC-Link when an interrupt occurs after the WM9715L has been put into sleep mode, see "Power Management") is enabled by the WAKEEN bit in register 58h. REGISTER ADDRESS 4Ch 56h BIT 2 2 LABEL GC2 GE2 DEFAULT 1 1 DESCRIPTION GENIRQ output enable GENIRQ is enabled when both GC4 and GE4 are set to `0'. To disable GENIRQ, set both bits to `1'. Other combinations (0/1, 1/0) are reserved. Inverts the GENIRQ signal (pin 45) 0: GENIRQ signal not inverted 1: GENIRQ signal inverted Enables WM9715L wake-up on interrupt 0: Disabled 1: Enabled
58h Additional Functional Control
0
IRQINV
0
1
WAKE EN
0
Table 36 Controlling the GENIRQ pin
The global interrupt signal GENIRQ is a logical OR of selected internal interrupts, each of which may have its polarity inverted and/or go through a "sticky" circuit if desired. This is illustrated below.
Figure 15 Interrupt Logic Equivalent Circuit Each GENIRQ interrupt source has an associated bit in register 54h for readback. INTERRUPT SOURCE Thermal Cutout (T) REG 54H BIT 11 DESCRIPTION Internal thermal cutout signal, indicates when internal temperature reaches approximately 150C (see "Thermal Sensor") Internal ADA (ADC Data Available) Signal enabled only when auxiliary ADC is active Internal PENDOWN Signal enabled only when pen-down detection is active Internal COMP2 output (Low Battery Alarm) enabled only when COMP2 is on Internal COMP1 output (Dead Battery Alarm) enabled only when COMP1 is on
AUXADC Data Available (A) Pen-down (P) COMP2 (C2) COMP1 (C1)
12 13 14 15
Table 37 Interrupt Sources
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Production Data below. REGISTER ADDRESS 4Eh LABEL DEFAULT DESCRIPTION
WM9715L
The processing of internal interrupt signals is controlled through registers 4Eh to 52h, as shown
Note: x identifies a particular interrupt (T, A, P, C2 or C1, as per Table 37) xP 1 Interrupt Polarity 0: Active Low 1: Active High [xI bit = internal interrupt signal XNOR xP] Interrupt Sticky 1: Sticky (GIn bit remains set until read, even after internal interrupt signal becomes inactive) 0: Not Sticky (GIn bit follows internal interrupt signal) Interrupt Enable 1: Wake Up (generate interrupts from this pin) 0: No wake-up (no interrupts generated) Interrupt Status Read: Returns status of each interrupt bit Write: Writing `0' clears sticky bit
50h
xS
0
52h
xW
0
54h
xI
N/A
Table 38 GENIRQ Interrupt Control The following procedure is recommended for handling GENIRQ interrupts: When the controller receives a GENIRQ interrupt, check register 54h. For each interrupt event in descending order of priority, check if the corresponding xI bit in 54h is `1'. If yes, execute corresponding interrupt routine, then write `0' to the xI bit. If no, continue to next lower priority interrupt. After all interrupts have been checked, check if the global interrupt is still asserted. If yes, repeat procedure. If no, jump back to process that ran before the interrupt.
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POWER MANAGEMENT
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The WM9715L includes the standard power down control register defined by the AC'97 specification (register 26h). Additionally, it also allows more specific control over the individual blocks of the device through register 24h. Each particular circuit block is active when both the relevant bit in register 26h AND the relevant bit in register 24h are set to `0'. REGISTER ADDRESS BIT LABEL DEFAULT NORMAL PWRUP PIN `HI' DURING RESET 1 (OFF) 1 (OFF) 1 (OFF) 1 (OFF) 1 (OFF) 1 (OFF) 1 (OFF) 0 0 0 0 Disables HPOUTL, HPOUTR and OUT3 Buffer Disables internal clock Disables AC-link interface (external clock off) Disables VREF, analogue mixers and outputs Disables analogue mixers, LOUT2, ROUT2 (but not VREF) Disables stereo DAC Disables audio ADCs and input Mux Read-only bit, indicates VREF is ready (inverse of PR2) Read-only bit, indicates analogue mixers are ready (inverse of PR3) Read-only bit, indicates audio DACs are ready (inverse of PR1) Read-only bit, indicates audio ADCs are ready (inverse of PR0) DESCRIPTION
26h Powerdown/ Status register
14 13 12 11 10 9 8 3 2 1 0
PR6 PR5 PR4 PR3 PR2 PR1 PR0 REF ANL DAC ADC
0 (ON) 0 (ON) 0 (ON) 0 (ON) 0 (ON) 0 (ON) 0 (ON) 1 1 1 1
Table 39 Powerdown and Status Register (Conforms to AC'97 Rev 2.2)
POWER-UP
As can be seen from the table above, most blocks are `ON' by default. However, if the PWRUP pin is held high during reset, the WM9715L starts up with all blocks powered down, saving power. This is achieved by connecting a pull-up resistor (e.g. 100k) from PWRUP to DBVDD. Note that the state of PWRUP during reset only affects register 26h.
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REGISTER ADDRESS 24h Additional power down control BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LABEL PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 DEFAULT 0 (ON) 0 (ON) 0 (ON) 0 (ON) 0 (ON) 0 (ON) 0 (ON) 0 (ON) 0 (ON) 0 (ON) 0 (ON) 0 (ON) 0 (ON) 0 (ON) 0 (ON) 0 (ON) DESCRIPTION Disables Crystal Oscillator Disables left audio DAC Disables right audio DAC Disables left audio ADC Disables right audio ADC Disables MICBIAS Disables left headphone mixer Disables right headphone mixer Disables speaker mixer Disables MONO_OUT buffer (pin 33) and phone mixer Disables OUT3 buffer (pin 37) Disables headphone buffers (HPOUTL/R) Disables speaker outputs (LOUT2, ROUT2) Disables Line Input PGA (left and right) * Disables Phone Input PGA * Disables Mic Input PGA (left and right) *
Table 40 Extended Power Down Register (Additional to AC'97 Rev 2.2) Note: *When disabling a PGA, always ensure that it is muted first.
ADDITIONAL POWER MANAGEMENT:
* * AUXDAC: see "Auxiliary DAC" section. AUXDAC is OFF by default. Touchpanel Interface: see "Controlling the Touchpanel Digitiser / Power Management". The touchpanel digitiser is OFF by default.
SLEEP MODE
Whenever the PR4 bit (reg. 26h) is set, the AC-Link interface is disabled, and the WM9715L is in sleep mode. There is in fact a very large number of different sleep modes, depending on the other control bits. For example, the low-power standby mode described below is a sleep mode. It is desirable to use sleep modes whenever possible, as this will save power. The following functions do not require a clock and can therefore operate in sleep mode: * * * * Analogue-to-analogue audio (DACs and ADCs unused), e.g. phone call mode Pen-down detection Interrupts Battery alarm / analogue comparators (but not battery measurement)
The WM9715L can awake from sleep mode as a result of * * A warm reset on the AC-Link (according to the AC'97 specification) An interrupt event such as pen-down, battery alarm, etc (if interrupt wake-up is enabled - see "Interrupt Control" section)
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LOW POWER STANDBY MODE
Production Data
If all the bits in registers 26h and 24h are set, then the WM9715L is in low-power standby mode and consumes very little current. A 1M resistor string remains connected across AVDD to generate VREF. This is necessary if the on-chip analogue comparators are used (see "Battery Alarm and Battery Measurement" section), and helps shorten the delay between wake-up and playback readiness. If VREF is not required, the 1M resistor string can be disabled by setting the SVD bit, reducing current consumption further. REGISTER ADDRESS 58h BIT 10 LABEL SVD DEFAULT 0 DESCRIPTION VREF Disable 0: VREF enabled using 1M string (low-power standby mode) 1 : VREF disabled, 1M string disconnected (OFF mode)
Table 41 Disabling VREF (for lowest possible power consumption)
SAVING POWER AT LOW SUPPLY VOLTAGES
The analogue supplies to the WM9715L can run from 1.8V to 3.6V. By default, all analogue circuitry on the IC is optimized to run at 3.3V. This set-up is also good for all other supply voltages down to 1.8V. However, at lower voltages, it is possible to save power by reducing the internal bias currents used in the analogue circuitry. This is controlled as shown below. REGISTER ADDRESS 5Ch BIT 6:5 LABEL VBIAS DEFAULT 00 DESCRIPTION Analogue Bias optimization 11 : Lowest bias current, optimized for 1.8V 10 : Low bias current, optimized for 2.5V 01, 00 : Default bias current, optimized for 3.3V
Table 42 Analogue Bias Selection
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UNUSED ANALOGUE INPUTS AND OUTPUTS
When analogue inputs or outputs are disabled, they remain internally connected to VREF (AVDD/2) through a large resistor. This maintains the potential at that node and helps to eliminate pops when the pins are re-enabled. There are several exceptions to this. Firstly, when VREF itself is disabled (PR3 = 1 in register 26h), unused analogue pins are not held at AVDD/2. Additionally: * The MIC1 input is disconnected from VREF if all of the following register settings are applied: PD0 = 1 in register 24h AND PR0 = 1 in register 26h AND MS = 00 in register 0Eh AND (RECSL = 000 or RECSR = 000 in register 1Ah) The MIC2 input is disconnected from VREF if all of the following register settings are applied: PD0 = 1 in register 24h AND PR0 = 1 in register 26h AND MS = 10 in register 0Eh AND (RECSL = 000 or RECSR = 000 in register 1Ah) The PCBEEP input is disconnected from VREF if PR2 = 1 in register 26h The PCBEEP input is also disconnected from VREF if the exact following register settings are applied: PD9 = 1 in register 24h or B2H = 1 in register 0Ah AND (PD8 = 1 in register 24h or B2H = 1 in register 0Ah) AND (PD7 = 1 in register 24h or B2S = 1 in register 0Ah) AND (PD6 = 1 in register 24h or B2P = 1 in register 0Ah)
*
* *
For MIC1 and MIC2, pop issues can be circumvented by disconnecting the microphone inputs from the record selector (RECSL = RECSR = 001 in register 1Ah) in sleep or standby modes. However, should it be necessary to maintain the VREF potential at MIC1, MIC2 or PCBEEP, this can be achieved by choosing any suitable register settings that are not identical to those shown above.
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WM9715L AC97 DATA AND CONTROL INTERFACE
INTERFACE PROTOCOL
Production Data
The WM9715Lhas a single AC'97 interface for both data transfer and control. The AC-Link uses 5 wires: * * * SDATAIN (pin 8) carries data from the WM9715L to the controller SDATAOUT (pin 5) carries data from the controller to the WM9715L BITCLK (pin 6) is a clock, normally generated by the WM9715L crystal oscillator and supplied to the controller. However, BITCLK can also be passed to the WM9715L from an off-chip generator. SYNC is a synchronization signal generated by the controller and passed to the WM9715L RESETB resets the WM9715L to its default state
* *
Figure 16 AC-Link Interface (typical case with BITCLK generated by the AC97 codec) The SDATAIN and SDATAOUT signals each carry 13 time-division multiplexed data streams (slots 0 to 12). A complete sequence of slots 0 to 12 is referred to as an AC-Link frame, and contains a total of 256 bits. The frame rate is 48kHz. This makes it possible to simultaneously transmit and receive multiple data streams (e.g. audio, touchpanel, AUXDAC, control) at sample rates up to 48kHz. Detailed information can be found in the AC'97 (Revision 2.2) specification, which can be obtained at http://www.intel.com/design/chipsets/audio/ Note: SDATAOUT and SYNC must be held low for when RESETB is applied. These signals must be held low for the entire duration of the RESETB pulse and especially during the low-to-high transition of RESETB. If either is set high during reset the AC'97 device may enter test modes. Information relating to this operation is available in the AC'97 specification or in Wolfson applications note WAN-0104 available at www.wolfsonmicro.com.
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INTERFACE TIMING
Test Characteristics: DBVDD = 3.3V, DCVDD = 3.3V, DGND1 = DGND2 = 0V, TA = -25C to +85C, unless otherwise stated.
CLOCK SPECIFICATIONS
tCLK_HIGH BITCLK tCLK_LOW
tCLK_PERIOD tSYNC_HIGH tSYNC_LOW
SYNC tSYNC_PERIOD
Figure 17 Clock Specifications (50pF External Load) PARAMETER BITCLK frequency BITCLK period BITCLK output jitter BITCLK high pulse width (Note 1) BITCLK low pulse width (Note 1) SYNC frequency SYNC period SYNC high pulse width SYNC low pulse width Note: 3 Worst case duty cycle restricted to 45/55 tSYNC_PERIOD tSYNC_HIGH tSYNC_LOW tCLK_HIGH tCLK_LOW 36 36 40.7 40.7 48 20.8 1.3 19.5 tCLK_PERIOD SYMBOL MIN TYP 12.288 81.4 750 45 45 MAX UNIT MHz ns ps ns ns kHz s s s
DATA SETUP AND HOLD
Figure 18 Data Setup and Hold (50pF External Load) Note: Setup and hold times for SDATAIN are with respect to the AC'97 controller, not the WM9715L. PARAMETER Setup to falling edge of BITCLK Hold from falling edge of BITCLK Output valid delay from rising edge of BITCLK SYMBOL tSETUP tHOLD tCO MIN 10 10 15 TYP MAX UNIT ns ns ns
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SIGNAL RISE AND FALL TIMES
triseCLK BITCLK triseSYNC SYNC triseDIN SDATAIN triseDOUT SDATAOUT tfallDOUT tfallDIN tfallSYNC tfallCLK
Production Data
Figure 19 Signal Rise and Fall Times (50pF External Load) PARAMETER SDATAOUT rise time SDATAOUT fall time SYNC rise time SYNC fall time BITCLK rise time BITCLK fall time SDATAIN rise time SDATAIN fall time SYMBOL triseDOUT tfallDOUT triseSYNC tfallSYNC triseCLK tfallCLK triseDIN tfallDIN MIN TYP MAX 6 6 6 6 6 6 6 6 UNIT ns ns ns ns ns ns ns ns
Incoming signals (from the AC'97 controller to the WM9715L)
Outgoing signals (from the WM9715L to the AC'97 controller)
AC-LINK POWERDOWN
SYNC
SLOT 1
SLOT 2
BITCLK
SDATAOUT
WRITE TO 0X20
DATA PR4
DON'T CARE
tS2_PDOWN SDATAIN
Figure 20 AC-Link Powerdown Timing AC-Link powerdown occurs when PR4 (register 26h, bit 12) is set (see "Power Management" section). PARAMETER End of Slot 2 to BITCLK and SDATAIN low SYMBOL tS2_PDOWN MIN TYP MAX 1.0 UNIT s
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COLD RESET (ASYNCHRONOUS, RESETS REGISTER SETTINGS)
tRST_LOW RESETB tRST2CLK
BITCLK
Figure 21 Cold Reset Timing Note: For correct operation SDATAOUT and SYNC must be held LOW for entire RESETB active low period otherwise the device may enter test mode. See AC'97 specification or Wolfson applications note WAN104 for more details.
PARAMETER RESETB active low pulse width RESETB inactive to BITCLK startup delay
SYMBOL tRST_LOW tRST2CLK
MIN 1.0 162.8
TYP
MAX
UNIT s ns
WARM RESET (ASYNCHRONOUS, PRESERVES REGISTER SETTINGS)
Figure 22 Warm Reset Timing PARAMETER SYNC active high pulse width SYNC inactive to BITCLK startup delay SYMBOL tSYNC_HIGH tRST2CLK 162.4 MIN TYP 1.3 MAX UNIT s ns
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WM9715L REGISTER MAP
Production Data
Note: Highlighted bits differ from the AC'97 specification (newly added for non-AC'97 function, or same bit used in a different way, or for another function)
Reg
00h 02h 04h 06h 08h 0Ah 0Ch 0Eh 10h 12h 14h 16h 18h 1Ah 1Ch 20h 22h 24h 26h Reset LOUT2/ROUT2 Volume Headphone Volume MONOOUT Volume DAC Tone Control PCBEEP Input PHONE Volume MIC Volume LINEIN Volume AUXDAC Volume / Routing Sidetone Volume OUT3 Volume DAC Volume Record Select Record Gain General Purpose DAC 3D Control Powerdown Powerdown Ctrl/Stat
Name
15
0 MU MU MU BB B2H P2H 0 L2H A2H STM MU D2H 0 RMU 0 0 PD15 0
14
SE4 0 0 0 0
13
SE3
12
SE2
11
SE1
10
SE0
9
ID9
8
ID8
7
ID7 ZC ZC
6
ID6 INV 0 0 DAT
5
ID5
4
ID4
3
ID3
2
ID2
1
ID1
0
ID0
Default
6174h 8000h 8000h 8000h 0F0Fh
LOUT2 Volume HPOUTL Volume 0 0 B2HVOL 0 BC B2S 0 0 0 0 0 BASS B2SVOL 0 0 0 0
ROUT2 Volume HPOUTR Volume 0 0 B2PVOL TC 0 0 MONOOUT Volume TRBL 0 0
ZC 0 B2P 0 20dB 0 A2P
AAA0h C008h 6808h E808h
P2S M12P L2S
0 M22P L2P A2HVOL STVOL
0 MS 0
0
PHONEIN Volume MICVOL (Mono /Right)
LMICVOL (Left Only) LINEINLVOL A2S ALCM 0 0 OUT3SRC A2SVOL ALCVOL SRC
0 A2PVOL 0 0 0
LINEINRVOL 0 0 0 0 AXE 0
AAA0h AD00h 8000h E808h 3000h 8000h
0 ZC 0 0 ZC 0 0 0 GRR 0 0 PD6 0
0
0 D2S BOOST GRL 0 0 PD14 PR6
0 D2P R2P
OUT3 Volume 0 0 0 Right DAC Volume 0 RECSR RECVOLR 0 0 0 0
Left DAC Volume R2P BST 0 0 PD11 PR3 RECSL RECVOLL 0 0 PD10 PR2 0 0 PD9 PR1 0 0 PD8 PR0
(Extended) 3DE 0 PD13 PR5 0 0 PD12 PR4
(Extended) 0 3DLC PD5 0 0 3DUC PD4 0 PD3 REF
LB 0 PD7 0
0000h 0000h
3DDEPTH PD2 ANL PD1 DAC PD0 ADC
0000h
Default for reg. 26h - pin 47 "low" Default for reg. 26h - pin 47 "high" during reset (recommended for lowest power) 28h 2Ah 2Ch 2Eh 32h 3Ah 4Ch 4Eh 50h 52h 54h 56h 58h 5Ah 5Ch 5Eh 60h 62h 64h Extended Audio ID Ext'd Audio stst/ctrl Audio DACs Sample Rate AUXDAC Sample Rate Audio ADCs Sample Rate SPDIF control Pin Configurations (1) Interrupt Polarity Interrupt Sticky Interrupt Wake-up Interrupt Flags Pin Configurations (2) Additional Functions (1) Vendor Reserved Add. Functions (2) Vendor Reserved ALC Control ALC / Noise Gate Control AUXDAC input control ALCL (target level) ALCSEL XSLE MAXGAIN AUXDACSLT
AMUTE C1 REF
000Fh FF00h 0 SPSA VRM 0 SPDIF SEN DRA 0 VRA VRA 0405h 0410h BB80h BB80h BB80h PRE GC5 1 0 0 0 GE5 0 GC4 1 0 0 0 GE4 0 GC3 1 0 0 0 GE3 COPY AUD IB PRO GC2 1 0 0 0 GE2 1 1 0 0 GI1 1 WAKE EN 0 1 0 0 0 0 IRQ INV 2000h F83Eh FFFFh 0000h 0000h interrupts F83Eh 0008h
ID1 0
ID0 0
0 0
0 0
REV1 0
REV0 SPCV
AMAP 0
LDAC 0
SDAC 0
CDAC 0
0
DACSR (Audio DACs Sample Rate) AUXDACSR (Auxiliary DAC Sample Rate) ADCSR (Audio ADCs Sample Rate) V 1 C1P C1S C1W C1I 1 DRS 1 C2P C2S C2W C2I 1 COMP2DEL 1 PP PS PW PI 1 SPSR 1 AP AS AW AI 1 0 L 1 TP TS TW TI 1 0 0 1 0 0 0 0 SVD 0 1 0 0 0 0 0 CC (Category Code) 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0
Die Revision
RESERVED FOR TEST C1SRC
C2 REF
C2SRC
DS
AMEN
VBIAS
ADCO
HPF
ENT
ASS
0000h
RESERVED FOR TEST HLD (hold time) ZC TIMEOUT ALC ZC NG AT DCY (decay time) 0 NGG ATK (attack time) NGTH (threshold) B032h 3E00h 0000h
AUXDAC VAL
66h- Vendor Reserved 74h 76h Digitiser Reg 1 78h 7Ah 7Ch 7Eh Digitiser Reg 2 Digitiser Read Back Vendor ID1 Vendor ID2
RESERVED. DO NOT WRITE TO THESE REGISTERS POLL PRP
PNDN
ADCSEL RPR ADCSRC 45W
COO PDEN
CTC 0
CR WAIT PIL 0 0
DEL
SLEN RPU
SLT
0006h 0001h 0000h 574Dh 4C12h
ADCD (TOUCHPANEL ADC DATA) ASCII character "M" "12" (indicates part family)
ASCII character "W" ASCII character "L"
Table 43 WM9715L Register Map
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Production Data
WM9715L
REGISTER BITS BY ADDRESS
Register 00h is a read-only register. Writing any value to this register resets all registers to their default, but does not change the contents of reg. 00h. Reading the register reveals information about the codec to the driver, as required by the AC'97 Specification, Revision 2.2 REG ADDR 00h BIT 14:10 9:6 5 4 3 2 1 0 LABEL SE [4:0] ID9:6 ID5 ID4 ID3 ID2 ID1 ID0 DEFAULT 11000 0101 1 1 0 1 0 0 DESCRIPTION Indicates a codec from Wolfson Microelectronics Indicates 18 bits resolution for ADCs and DACs Indicates that the WM9715L supports bass boost Indicates that the WM9715L has a headphone output Indicates that the WM9715L does not support simulated stereo Indicates that the WM9715L supports bass and treble control Indicates that the WM9715L does not support modem functions Indicates that the WM9715L does not have a dedicated microphone ADC REFER TO Intel's AC'97 Component Specification, Revision 2.2, page 50
Register 02h controls the output pins LOUT2 and ROUT2. REG ADDR 02h BIT 15 13:8 7 6 5:0 MU LOUT2 VOL ZC INV ROUT2 VOL LABEL DEFAULT 1 (mute) 000000 (0dB) 0 (OFF) 0 (not inverted) 000000 (0dB) DESCRIPTION Mutes LOUT2 and ROUT2. LOUT2 volume Enables zero-cross detector Inverts LOUT2 (for BTL speaker operation) ROUT2 volume REFER TO Analogue Audio Outputs
Register 04h controls the headphone output pins, HPOUTL and HPOUTR. REG ADDR 04h BIT 15 13:8 7 5:0 MU HPOUTL VOL ZC HPOUTR VOL LABEL DEFAULT 1 (mute) 000000 (0dB) 0 (OFF) 000000 (0dB) DESCRIPTION Mutes HPOUTL and HPOUTR. HPOUTL volume Enables zero-cross detector HPOUTR volume REFER TO Analogue Audio Outputs
Register 06h controls the analogue output pin MONOOUT. REG ADDR 06h 7 5:0 BIT 15 MU ZC MONOOUT VOL LABEL DEFAULT 1 (mute) 0 (OFF) 000000 (0dB) Mutes MONOOUT. Enables zero-cross detector MONOOUT volume DESCRIPTION REFER TO Analogue Audio Outputs
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WM9715L
Register 08h controls the bass and treble response of the left and right audio DAC (but not AUXDAC). REG ADDR 08h BIT 15 12 11:8 6 4 3:0 BB BC BASS DAT TC TRBL LABEL DEFAULT 0 (linear) 0 (low) 1111 (OFF) 0 (OFF) 0 (high) 1111 (OFF) DESCRIPTION Selects linear bass control or adaptive bass boost Selects bass cut-off frequency Controls bass intensity Enables 6dB pre-DAC attenuation Selects treble cut-off frequency Controls treble intensity
Production Data
REFER TO Audio DACs, Tone Control / Bass Boost
Register 0Ah controls the analogue input pin PCBEEP. REG ADDR 0Ah BIT 15 14:12 11 10:8 7 6:4 LABEL B2H B2HVOL B2S B2SVOL B2P B2PVOL DEFAULT 1 (mute) 010 (0dB) 1 (mute) 010 (0dB) 1 (mute) 010 (0dB) DESCRIPTION Mutes PCBEEP to headphone mixer path Controls gain of PCBEEP to headphone mixer path Mutes PCBEEP to speaker mixer path Controls gain of PCBEEP to speaker mixer path Mutes PCBEEP to phone mixer path Controls gain of PCBEEP to phone mixer path REFER TO Analogue Inputs, PCBEEP Input
Register 0Ch controls the analogue input pin PHONE. REG ADDR 0Ch BIT 15 14 4:0 LABEL P2H P2S PHONEVOL DEFAULT 1 (mute) 1 (mute) 01000 (0dB) DESCRIPTION Mutes PHONE to headphone mixer path Mutes PHONE to speaker mixer path Controls PHONE input gain to all mixers (but not to ADC) REFER TO Analogue Inputs, PHONE Input
Register 0Eh controls the analogue input pins MIC1 and MIC2. REG ADDR 0Eh BIT 14 13 12:8 7 6:5 4:0 LABEL M12P M22P LMICVOL 20dB MS MICVOL DEFAULT 1 (mute) 1 (mute) 01000 (0dB) 0 (OFF) 00 (MIC1 only) 01000 (0dB) DESCRIPTION Mutes MIC1 to phone mixer path Mutes MIC2 to phone mixer path Controls volume of MIC1 (left), in stereo mode only Enables 20dB gain boost Selects microphone mode. 00=MIC1 only, 01=differential, 10=MIC2 only, 11=stereo Controls mic volume (except MIC1 in stereo mode) REFER TO Analogue Inputs, Microphone Input
Register 10h controls the analogue input pins LINEINL and LINEINR. REG ADDR 10h BIT 15 14 13 12:8 4:0 LABEL L2H L2S L2P LINEINLVOL LINEINRVOL DEFAULT 1 (mute) 1 (mute) 1 (mute) 01000 (0dB) 01000 (0dB) DESCRIPTION Mutes LINEIN to headphone mixer path Mutes LINEIN to speaker mixer path Mutes LINEIN to phone mixer path Controls LINEINL input gain to all mixers (but not to ADC) Controls LINEINR input gain to all mixers (but not to ADC) REFER TO Analogue Inputs, Line Input
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Production Data Register 12h controls the output signal of the auxiliary DAC. REG ADDR 12h BIT 15 14:12 11 10:8 7 6:4 0 LABEL A2H A2HVOL A2S A2SVOL A2P A2PVOL AXE DEFAULT 1 (mute) 010 (0dB) 1 (mute) 010 (0dB) 1 (mute) 010 (0dB) 0 (0FF) DESCRIPTION Mutes AUXDAC to headphone mixer path Controls gain of AUXDAC to headphone mixer path Mutes AUXDAC to speaker mixer path Controls gain of AUXDAC to speaker mixer path Mutes AUXDAC to phone mixer path Controls gain of AUXDAC to phone mixer path Enables AUXDAC
WM9715L
REFER TO Auxiliary DAC
Register 14h controls the side tone paths. REG ADDR 14h BIT 15 14:12 11:10 9:7 LABEL STM STVOL ALCM ALCVOL DEFAULT 1 (mute) 010 (0dB) 11 (mute both) 010 (0dB) DESCRIPTION Mutes microphone to headphone mixer path Controls gain of microphone to headphone mixer path Selects ALC to headphone mixer path. 00=stereo, 01=right only, 10=left only, 11=mute both left and right Controls gain of ALC to headphone mixer path REFER TO Audio Mixers, Side Tone Control
Register 16h controls the analogue output pin OUT3, and also contains one control bit that affects LOUT2 and ROUT2. REG ADDR 16h BIT 15 10:9 8 7 5:0 MU OUT3SRC SRC ZC OUT3VOL LABEL DEFAULT 1 (mute) 00 (-HPOUTR) 0 (spkr mix) 0 (disabled) 000000 (0dB) Mutes OUT3. Selects source of OUT3 signal. 00=-HPOUTR, 01=VREF, 10=HPOUTL+HPOUTR, 11=-MONOOUT Selects source of LOUT2 and ROUT2 signals. 0=from speaker mixer, 1=from headphone mixer Zero-cross enable OUT3 volume DESCRIPTION REFER TO Analogue Audio Outputs
Register 18h controls the audio DACs (but not AUXDAC). REG ADDR 18h BIT 15 14 13 12:8 4:0 LABEL D2H D2S D2P LDACVOL RDACVOL DEFAULT 1 (mute) 1 (mute) 1 (mute) 01000 (0dB) 01000 (0dB) DESCRIPTION Mutes DAC to headphone mixer path Mutes DAC to speaker mixer path Mutes DAC to phone mixer path Controls left DAC input gain to all mixers Controls right DAC input gain to all mixers REFER TO Audio DACs
Register 1Ah controls the record selector and the ADC to phone mixer path. REG ADDR 1Ah BIT 14 13:12 11 10:8 2:0 LABEL BOOST R2P R2PBST RECSL RECSR DEFAULT 0 (OFF) 11 (mute) 0 (OFF) 000 (mic) 000 (mic) DESCRIPTION Enables 20dB gain boost for recording Controls ADC to phone mixer path. 00=stereo, 01=left ADC only, 10=right ADC only, 11=mute left and right Enables 20dB gain boost for ADC to phone mixer path Selects left ADC signal source Selects right ADC signal source REFER TO Audio ADC, Record Selector
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WM9715L
Register 1Ch controls the.recording gain. REG ADDR 1Ch BIT 15 14 13:8 7 6 5:0 LABEL RMU GRL RECVOLL ZC GRR RECVOLR DEFAULT 1 (mute) 0 (standard) 000000 (0dB) 0 (OFF) 0 (standard) 000000 (0dB) DESCRIPTION Mutes audio ADC input Selects gain range for PGA of left ADC. 0=0...+22.5dB in 1.5dB steps, 1=-17.25...+30dB in 0.75dB steps Controls left ADC recording volume Enables zero-cross detector Selects gain range for PGA of left ADC. 0=0...+22.5dB in 1.5dB steps, 1=-17.25...+30dB in 0.75dB steps Controls right ADC recording volume
Production Data
REFER TO Audio ADC, Record Gain
Register 20h is a "general purpose" register as defined by the AC'97 specification. Only two bits are implemented in the WM9715L. REG ADDR 20h BIT 13 7 LABEL 3DE LB DEFAULT 0 (OFF) 0 (OFF) DESCRIPTION Enables 3D enhancement Enables loopback (i.e. feed ADC output data directly into DAC) REFER TO Audio DACs, 3D Stereo Enhancement Intel's AC'97 Component Specification, Revision 2.2, page 55
Register 22h controls 3D stereo enhancement for the audio DACs. REG ADDR 22h 5 4 3:0 BIT LABEL 3DLC 3DUC 3DDEPTH DEFAULT 0 (low) 0 (high) 0000 (0%) DESCRIPTION Selects lower cut-off frequency Selects upper cut-off frequency Controls depth of 3D effect REFER TO Audio DACs, 3D Stereo Enhancement
Register 24h is for power management additional to the AC'97 specification. Note that the actual state of each circuit block depends on both register 24h AND register 26h. REG ADDR 24h BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LABEL PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 DEFAULT 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* Disables Crystal Oscillator Disables left audio DAC Disables right audio DAC Disables left audio ADC Disables right audio ADC Disables MICBIAS Disables left headphone mixer Disables right headphone mixer Disables speaker mixer Disables MONO_OUT buffer (pin 33) and phone mixer Disables OUT3 buffer (pin 37) Disables headphone buffers (HPOUTL/R) Disables speaker outputs (LOUT2, ROUT2) Disables Line Input PGA (left and right) Disables Phone Input PGA Disables Mic Input PGA (left and right) DESCRIPTION REFER TO Power Management
* "0" corresponds to "ON", if and only if the corresponding bit in register 26h is also 0.
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Production Data
WM9715L
Register 26h is for power management according to the AC'97 specification. Note that the actual state of many circuit blocks depends on both register 24h AND register 26h. REG ADDR BIT 14 13 12 11 10 9 8 3 2 1 0 LABEL PR6 PR5 PR4 PR3 PR2 PR1 PR0 REF ANL DAC ADC inverse of PR2 inverse of PR3 inverse of PR1 inverse of PR0 DEFAULT see note DESCRIPTION Disables HPOUTL, HPOUTR and OUT3 Buffer Disables Internal Clock Disables AC-link interface (external clock off) Disables VREF, analogue mixers and outputs Disables analogue mixers, LOUT2, ROUT2 (but not VREF) Disables Stereo DAC and AUXDAC Disables audio ADCs and input Mux Read-only bit, Indicates VREF is ready Read-only bit, indicates analogue mixers are ready Read-only bit, indicates audio DACs are ready Read-only bit, indicates audio ADCs are ready REFER TO Power Management
Note: PR6 to PR0 default to 1 if the PWRUP pin is held high during reset, otherwise they default to 0. Register 28h is a read-only register that indicates to the driver which advanced AC'97 features the WM9715L supports. REG ADDR 28h BIT 15:14 11:10 9 8 7 6 3 2 1 0 LABEL ID REV AMAP LDAC SDAC CDAC VRM SPDIF DRA VRA DEFAULT 00 01 0 0 0 0 0 1 0 1 DESCRIPTION Indicates that the WM9715L is configured as the primary codec in the system. Indicates that the WM9715L conforms to AC'97 Rev2.2 Indicates that the WM9715L does not support slot mapping Indicates that the WM9715L does not have an LFE DAC Indicates that the WM9715L does not have Surround DACs Indicates that the WM9715L does not have a Centre DAC Indicates that the WM9715L does not have a dedicated, variable rate microphone ADC Indicates that the WM9715L supports SPDIF output Indicates that the WM9715L does not support double rate audio Indicates that the WM9715L supports variable rate audio REFER TO Intel's AC'97 Component Specification, Revision 2.2, page 59
Register 2Ah controls the SPDIF output and variable rate audio. REG ADDR 2Ah BIT 10 5:4 2 0 LABEL SPCV SPSA SEN VRA DEFAULT 1 (valid) 01 (slots 6, 9) 0 (OFF) 0 (OFF) DESCRIPTION SPDIF validity bit (read-only) Controls SPDIF slot assignment. 00=slots 3 and 4, 01=6/9, 10=7/8, 11=10/11 Enables SPDIF_OUT pin (note that GC5 in register 4Ch and GE5 in register 56h must also be set to 0) Enables variable rate audio REFER TO Digital Audio (SPDIF) Output
Registers 2Ch, 2Eh 32h and control the sample rates for the stereo DAC, auxiliary DAC and audio ADC, respectively. REG ADDR 2Ch 2Eh 32h BIT all all all LABEL DACSR AUXDACSR ADCSR DEFAULT BB80h BB80h BB80h DESCRIPTION Controls stereo DAC sample rate Controls auxiliary DAC sample rate Controls audio ADC sample rate REFER TO Variable Rate Audio / Sample Rate Conversion
Note: The VRA bit in register 2Ah must be set first to obtain sample rates other than 48kHz
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WM9715L
Register 3Ah controls the SPDIF output. REG ADDR 3Ah BIT 15 14 13:12 11 10:4 3 2 1 0 V DRS SPSR L CC PRE COPY AUDIB PRO LABEL 0 0 10 0 0000000 0 0 0 0 DEFAULT DESCRIPTION Validity bit; `0' indicates frame valid, `1' indicates frame not valid Indicates that the WM9715L does not support double rate SPDIF output (read-only) Indicates that the WM9715L only supports 48kHz sampling on the SPDIF output (read-only) Generation level; programmed as required by user Category code; programmed as required by user Pre-emphasis; `0' indicates no pre-emphasis, `1' indicates 50/15us pre-emphasis Copyright; `0' indicates copyright is not asserted, `1' indicates copyright Non-audio; `0' indicates data is PCM, `1' indicates nonPCM format (e.g. DD or DTS) Professional; `0' indicates consumer, `1' indicates professional
Production Data
REFER TO Digital Audio (SPDIF) Output
Register 4Ch (together with register 56h) controls the outputs ADCIRQ, PENDOWN, GENIRQ and SPDIF_OUT. REG ADDR 4Ch 5 4 3 2 BIT LABEL GC5 GC4 GC3 GC2 DEFAULT 1 (off) 1 (off) 1 (off) 1 (off) DESCRIPTION `0' enables the SPDIF_OUT pin (note that GE5 in register 56h must also be set to 0, and SEN in register 2Ah to 1) `0' enables the ADCIRQ pin (note that GE4 in register 4Ch must also be set to 0). `0' enables the PENDOWN pin (note that GE3 in register 4Ch must also be set to 0). `0' enables the GENIRQ pin (note that GE2 in register 4Ch must also be set to 0). REFER TO Interrupt Control
Register 4Eh to 54h control the processing of GENIRQ interrupt signals. REG ADDR 4Eh 50h 52h 54h please refer to the register map BIT LABEL DEFAULT all 1 all 0 (not sticky) all 0 (OFF) = status of internal interrupt signal DESCRIPTION Controls interrupt polarity Makes interrupt bits sticky Enables wake-up for each interrupt Interrupt status (read from inputs, write `0' to clear sticky bits) REFER TO Interrupt Control
15 14 13 12 11
Controls Comparator 1 interrupts Controls Comparator 2 interrupts Controls Pen-Down interrupts Controls AUXADC data available interrupts Controls Thermal sensor interrupts
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Production Data Register 56h (together with register 4Ch) controls the outputs ADCIRQ, PENDOWN, GENIRQ and SPDIF_OUT. REG ADDR 56h 5 4 3 2 BIT LABEL GE5 GE4 GE3 GE2 DEFAULT 1 (off) 1 (off) 1 (off) 1 (off) DESCRIPTION `0' enables the SPDIF_OUT pin (note that GC5 in register 4Ch must also be set to 0, and SEN in register 2Ah to 1) `0' enables the ADCIRQ pin (note that GC4 in register 4Ch must also be set to 0). `0' enables the PENDOWN pin (note that GC3 in register 4Ch must also be set to 0). `0' enables the GENIRQ pin (note that bit GC2 in register 4Ch must also be set to 0).
WM9715L
REFER TO Interrupt Control
Register 58h controls several additional functions. REG ADDR 58h BIT 15:13 10 3:2 1 0 LABEL COMP2DEL SVD DIE REV WAKEEN IRQ INV DEFAULT 000 (no delay) 0 (enabled) DESCRIPTION Selects Comparator 2 delay Disables VREF for lowest possible power consumption Enables GENIRQ interrupt wake-up Inverts the GENIRQ signal (pin 45) REFER TO Battery Alarm Power Management N/A Interrupt Control
Indicates device revision. 00=Rev.A, 01=Rev.B, 10=Rev.C 0 (no wake-up) 0 (not inverted)
Register 5Ch controls several additional functions. REG ADDR 5Ch BIT 15 14 13:12 11 10:9 8 7 6:5 4 3 2 1:0 LABEL AMUTE C1REF C1SRC C2REF C2SRC DS AMEN VBIAS ADCO HPF ENT ASS DEFAULT 0 0 (AVDD/2) 00 (OFF) 0 (AVDD/2) 00 (OFF) 0 0 (OFF) 00 0 0 0 00 DESCRIPTION Read-only bit to indicate DAC auto-muting Selects Comparator 1 Reference Voltage Selects Comparator 1 Signal Source Selects Comparator 1 Reference Voltage Selects Comparator 1 Signal Source Selects differential microphone input pins. 0=MIC1 and MIC2, 1=LINEL and LINER Enables DAC Auto-Mute Selects analogue bias for lowest power, depending on AVDD supply. 0X=3.3V, 10=2.5V, 11=1.8V Selects source of SPDIF data. 0=from SDATAOUT, 1= from audio ADC Disables ADC high-pass filter Enables thermal sensor Selects time slots for stereo ADC data. 00=slots 3 and 4, 01=7/8, 10=6/9, 11=10/11 Power Management Digital Audio (SPDIF) Output Audio ADC Analogue Audio Outputs, Thermal Sensor Audio ADC, ADC Slot Mapping Analogue Inputs, Microphone Input REFER TO Audio DACs, Stereo DACs Battery Alarm
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WM9715L
Registers 60h and 62h control the ALC and Noise Gate functions. REG ADDR 60h BIT 15:12 11:8 7:4 3:0 62h 15:14 13:11 10:9 8 7 5 4:0 LABEL ALCL HLD DCY ATK ALCSEL MAXGAIN ZC TIMEOUT ALCZC NGAT NGG NGTH DEFAULT 1011 (-12dB) 0000 (0 ms) 0011 (192 ms) 0010 (24 ms) 00 (OFF) 111 (+30dB) 11 (slowest) 0 (OFF) 0 (OFF) 0 (hold gain) 00000 (-76.5dB) DESCRIPTION Controls ALC threshold Controls ALC hold time Controls ALC decay time Controls ALC attack time Controls which channel ALC operates on. 00=none, 01=right only, 10=left only, 11=both Controls upper gain limit for ALC Controls time-out for zero-cross detection Enables zero-cross detection for ALC Enables noise gate function Selects noise gate type. 0=hold gain, 1=mute Controls noise gate threshold
Production Data
REFER TO Audio ADC, Automatic Level Control
Register 64h controls the input signal of the auxiliary DAC. REG ADDR 64h BIT 15 14:12 11:0 LABEL XSLE AUXDACSLT AUXDACVAL DEFAULT 0 000 (Slot 5) 000000000 DESCRIPTION Selects input for AUXDAC. 0=from AUXDACVAL (for DC signals), 1=from AC-Link slot (for AC signals) Selects input slot for AUXDAC (with XSLE=1) AUXDAC Digital Input for AUXDAC (with XSLE=0). 000h= minimum, FFFh=full-scale REFER TO Auxiliary DAC
Registers 76h, 78h and 7Ah control the touchpanel interface. REG ADDR 76h BIT 15 14:12 11 10 9:8 7:4 3 2:0 78h 15:14 13 12 11 9 8 5:0 7Ah read only 15 14:12 11:0 LABEL POLL ADCSEL COO CTC CR DEL SLEN SLT PRP RPR 45W PDEN WAIT PIL RPU PNDN ADCSRC ADCD 0 000 (none) 0 (OFF) 0 (polling) 00 (93.75Hz) 0000 (20.8s) 1 10 00 0 0 (4-wire) 0 (always) 0 0 (200A) 000001 (68k) 0 (pen up) 000 (none) 000h DEFAULT DESCRIPTION Writing "1" starts a measurement (this bit resets itself) Selects measurement type Enables co-ordinate mode Enables continuous conversions Controls conversion rate in continuous mode Controls touchpanel settling time Enables slot readback of touchpanel data Selects time slot for readback of touchpanel data Selects mode of operation. 00=OFF, 01=pen detect with wake-up, 10=pen detect without wake-up, 11=running Selects wake-up mode. 0=AC-Link only, 1=AC-Link and WM9715L auto-wake-up Selects 4-wire or 5-wire touchpanel Selects when touchpanel measurements take place. 0=always, 1=only when pen is down Controls data readback from register 7Ah. 0=overwrite old data with new, 1=wait until old data has been read Controls current used for pressure measurement. 1=400A Controls internal pull-up resistor for pen-down detection Indicates pen status. Indicates measurement type Returns data from touchpanel / AUXADC REFER TO Touchpanel Interface
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Production Data Register 7Ch and 7Eh are read-only registers that indicate the device family to the driver. REG ADDR 7Ch 7Eh BIT 15:8 7:0 15:8 7:0 LABEL F7:0 S7:0 T7:0 REV7:0 DEFAULT 57h 4Dh 4Ch 12h DESCRIPTION ASCII character "W" for Wolfson ASCII character "M" ASCII character "L" Part family identifier
WM9715L
REFER TO Intel's AC'97 Component Specification, Revision 2.2, page 50
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WM9715L APPLICATIONS INFORMATION
RECOMMENDED EXTERNAL COMPONENTS
Production Data
Figure 23 External Components Diagram
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Production Data
WM9715L
RECOMMENDED COMPONENTS VALUES
COMPONENT REFERENCE C1 - C6 C7 - C8 C9 C10 C11 C12 C13 C14 C27 & C28 C15 - C20 C21 - C23 C24 - C26 R1 XT SUGGESTED VALUE 100nF 10uF 100nF 10uF 100nF 10uF 100nF 10uF 22pF 1uF 2.2uF 220F 100k 24.576MHz DESCRIPTION De-coupling for DBVDD,DCVDD,TPVDD,AVDD,SPKVDD,HPVDD Reservoir capacitor for DVDD, AVDD. Should the supplies use separate sources then additional capacitors will be required of each additional source. De-coupling for CAP2. Reservoir capacitor for CAP2 De-coupling for VREF Reservoir capacitor for VREF De-coupling for MICBIAS - Not required if MICBIAS output is not used Reservoir capacitor for MICBIAS - Not required if MICBIAS output is not used Required when used with a parallel resonant crystal. AC coupling capacitors Output AC coupling capacitors to remove VREF DC level from outputs Output AC coupling capacitors to remove VREF DC level from outputs. Pull-up resistor, ensures that all circuit blocks are OFF by default AC'97 master clock frequency. A bias resistor is not required but if connected will not affect operation if the value is large (above 1M)
Table 44 External Components Descriptions Note: 3 For Capacitors C7, C8, C10, C12 and C14 it is recommended that very low ESR components are used.
LINE OUTPUT
The headphone outputs, HPOUTL and HPOUTR, can be used as stereo line outputs. The speaker outputs, LOUT2 and ROUT2, can also be used as line outputs, if LOUT2 is not inverted for BTL operation (INV = 0). Recommended external components are shown below.
Figure 24 Recommended Circuit for Line Output The DC blocking capacitors and the load resistance together determine the lower cut-off frequency, fc. Assuming a 10 k load and C1, C2 = 10F: fc = 1 / 2 (RL+R1) C1 = 1 / (2 x 10.1k x 1F) = 16 Hz Increasing the capacitance lowers fc, improving the bass response. Smaller values of C1 and C2 will diminish the bass response. The function of R1 and R2 is to protect the line outputs from damage when used improperly.
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WM9715L
AC-COUPLED HEADPHONE OUTPUT
Production Data
The circuit diagram below shows how to connect a stereo headphone to the WM9715L.
Figure 25 Simple Headphone Output Circuit Diagram The DC blocking capacitors C1 and C2 together with the load resistance determine the lower cut-off frequency, fc. Increasing the capacitance lowers fc, improving the bass response. Smaller capacitance values will diminish the bass response. For example, with a 16 load and C1 = 220F: fc = 1 / 2 RLC1 = 1 / (2 x 16 x 220F) = 45 Hz
DC COUPLED (CAPLESS) HEADPHONE OUTPUT
In the interest of saving board space and cost, it may be desirable to eliminate the 220F DC blocking capacitors. This can be achieved by using OUT3 as a headphone pseudo-ground, as shown below.
Figure 26 Capless Headphone Output Circuit Diagram (OUT3SRC = 10) As the OUT3 pin produces a DC voltage of AVDD/2, there is no DC offset between HPOUTL/HPOUTR and OUT3, and therefore no DC blocking capacitors are required. However, this configuration has some drawbacks: * * The power consumption of the WM9715L is increased, due to the additional power consumed in the OUT3 output buffer. If the DC coupled output is connected to the line-in of a grounded piece of equipment, then OUT3 becomes short-circuited. Although the built-in short circuit protection will prevent any damage to the WM9715L, the audio signal will not be transmitted properly. OUT3 cannot be used for another purpose
*
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Production Data
WM9715L
LOUT2 and ROUT2 can differentially drive a mono 8 loudspeaker as shown below.
BTL LOUDSPEAKER OUTPUT
Figure 27 Speaker Output Connection (INV = 1) The right channel is inverted by setting the INV bit, so that the signal across the loudspeaker is the sum of left and right channels.
COMBINED STEREO HEADSET / BTL EAR SPEAKER
In smartphone applications with a loudspeaker and separate ear speaker (receiver), a BTL ear speaker can be connected at the OUT3 pin, as shown below.
Figure 28 Combined Headset / BTL Ear Speaker (OUT3SRC = 00) The ear speaker and the stereo headset play the same signal. Whenever the headset is plugged in, the headphone outputs are enabled and OUT3 disabled. When the headset is not plugged in, OUT3 is enabled. This requires the use of a headset jack with a built-in mechanical switch, connected to a GPIO pin on the system CPU. Depending on the state of the switch, the GPIO pin is either grounded or high (due to a pull-up resistor). Whenever the CPU detects a change in the GPIO logic level, it should update the WM9715L registers to enable / disable the appropriate analogue outputs.
COMBINED HEADSET / SINGLE-ENDED EAR SPEAKER
Instead of a BTL ear speaker, a single-ended ear speaker can also be used, as shown below.
Figure 29 Combined Headset / Single-ended Ear Speaker (OUT3SRC = 01)
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WM9715L PACKAGE DIMENSIONS
FL: 48 PIN QFN PLASTIC PACKAGE 7 X 7 X 0.9 mm BODY, 0.50 mm LEAD PITCH
D2 D2/2 37 48 L 36 1 INDEX AREA (D/2 X E/2)
Production Data
DM029.E
SEE DETAIL 1
D
EXPOSED GROUND 6 PADDLE
E2/2
E2 SEE DETAIL 2
E
25
12 2X b 2X aaa C aaa C
24 e
13
BOTTOM VIEW
TOP VIEW
ccc C (A3) A 0.08 C
C
SEATING PLANE
SIDE VIEW
A1
DETAIL 1
R = 0.3MM EXPOSED GROUND PADDLE
DETAIL 2
Datum Terminal tip e/2 e R
1
DETAIL 3
W T (A3) H b Exposed lead G
Half etch tie bar
DETAIL 3
Symbols A A1 A3 b D D2 E E2 e G H L T W aaa bbb ccc REF
Dimensions (mm) NOM MAX 0.90 1.00 0.05 0.02 0.20 REF 0.18 0.25 0.30 7.00 BSC 5.00 5.15 5.25 7.00 BSC 5.00 5.15 5.25 0.5 BSC 0.213 0.1 0.50 0.30 0.4 0.1 0.2 Tolerances of Form and Position 0.15 0.10 0.10 MIN 0.80 0
NOTE
1
JEDEC, MO-220, VARIATION VKKD-2
NOTES: 1. DIMENSION b APPLIED TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.15 mm AND 0.30 mm FROM TERMINAL TIP. 2. ALL DIMENSIONS ARE IN MILLIMETRES 3. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1 SPP-002. 4. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS. 5. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. 6. REFER TO APPLICATION NOTE WAN_0118 FOR FURTHER INFORMATION REGARDING PCB FOOTPRINTS AND QFN PACKAGE SOLDERING.
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Production Data
WM9715L
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